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VERTICAL CONDUCTING CONNECTION TO A POLY-Si TRENCH IN Si

IP.com Disclosure Number: IPCOM000035004D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Lu, NC: AUTHOR [+2]

Abstract

Current processing techniques in the microelectronics industry are capable of embedding a poly-Si trench within single crystal Si. The steps for doing this are shown in Fig. 1. Fig. 1A depicts an etched trench 10 in Si 12 having a SiO2/Si3N4/SiO2 lining 14. Trench 10 is filled by deposition of heavily doped poly-Si 16 (Fig. 1B), followed by chemical-mechanical polishing to remove the excess Si on the surface, resulting in an planarized surface 18, as shown in Fig. 1C. The surface is then oxidized so that the poly-Si is covered by thick SiO2, layer 20. Very little oxide will grow on the surrounding Si surface because the Si3N4 film will act as a growth barrier. By chemical etching, the nitride on the Si surface will be removed.

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VERTICAL CONDUCTING CONNECTION TO A POLY-Si TRENCH IN Si

Current processing techniques in the microelectronics industry are capable of embedding a poly-Si trench within single crystal Si. The steps for doing this are shown in Fig. 1. Fig. 1A depicts an etched trench 10 in Si 12 having a SiO2/Si3N4/SiO2 lining 14. Trench 10 is filled by deposition of heavily doped poly-Si 16 (Fig. 1B), followed by chemical-mechanical polishing to remove the excess Si on the surface, resulting in an planarized surface 18, as shown in Fig. 1C. The surface is then oxidized so that the poly-Si is covered by thick SiO2, layer 20. Very little oxide will grow on the surrounding Si surface because the Si3N4 film will act as a growth barrier. By chemical etching, the nitride on the Si surface will be removed. Although part of

(Image Omitted)

the oxide on the poly-Si surface will be removed at the same time, some will be left behind because it is thicker and high selectivity between nitride and oxide layers can be achieved using reactive ion etching (RIE) (Fig. 1D). An epi-Si layer 22 can be grown on the exposed Si surface as well as on the oxidized trench surface. The latter is achieved by the so-called SOI (Si on Insulator) technique to provide the final structure shown in Fig. 1E. The trench structure has a potential application in dynamic random access memory (DRAM) chips. A schematic of a memory cell configuration is depicted in Fig. 2A. In this device, the n+ poly-Si trench 24 used as a capacitor is placed directly beneath the n+ drain region 26. A key processing step is to electrically join the n+ poly-Si trench 24 to the n+ single crystal Si drain region 26. The challenging problem is how to break open or remove the oxide layer on top of the trench. If a contact area is opened on the trench before the growth of the epi-Si layer, a poly-Si layer will grow from the trench to compete with the epi-Si from th...