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Base Register Buffer to Eliminate Address Generation Time in IBM System/370 Architectures

IP.com Disclosure Number: IPCOM000035008D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Goyal, A: AUTHOR [+2]

Abstract

A base register buffer mechanism is described herein which shortens the execution time of most RX, RS, SS, SSE, SI, and S instructions in the IBM System/370 processors by decoding the instruction and doing the address generation for a memory operand concurrently. In most programs a single register is used as the base register repeatedly, and its contents change rather infrequently. While generating memory addresses, the time required for fetching the contents of the base register from the register file can be eliminated from the execution time of the instruction, if the address generation unit could save the contents of the base register it uses, and reuse this value whenever possible. The figure shows the proposed base-register buffer mechanism.

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Base Register Buffer to Eliminate Address Generation Time in IBM System/370 Architectures

A base register buffer mechanism is described herein which shortens the execution time of most RX, RS, SS, SSE, SI, and S instructions in the IBM System/370 processors by decoding the instruction and doing the address generation for a memory operand concurrently. In most programs a single register is used as the base register repeatedly, and its contents change rather infrequently. While generating memory addresses, the time required for fetching the contents of the base register from the register file can be eliminated from the execution time of the instruction, if the address generation unit could save the contents of the base register it uses, and reuse this value whenever possible. The figure shows the proposed base-register buffer mechanism. The hardware components present, beyond those that are found in traditional processors, include a 36-bit buffer 1 comprising a 4-bit register address part and a 32-bit data (value) part; two 4-bit comparators 2, 3; a 32-bit 2-to-1 multiplexer 4; and some random logic (not shown). An extra adder 5 has been shown for clarity, but it can be multiplexed with the adder 6 already present. On every instruction fetch, it is assumed that the second half- word of the instruction contains the base and the displacement value, that the index register is 0 if the instruction is of RX format, and that the contents of the correct base register are stored in the base register buffer. These assumptions are verified by comparator 3 and the 'AND...