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CMOS Self-Timed Sense Amplifier Circuit

IP.com Disclosure Number: IPCOM000035011D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Chappell, BA: AUTHOR [+3]

Abstract

A sense amplifier for static random-access memories using complementary metal oxide semiconductors and timed from the accessed wordline provides reliable, high-speed operation over wide parameter variations using a setting signal with slow and fast setting slopes and decoupling devices. In Fig. 1, assume row decoder 1 and column decoder 2 are selected for a read. Wordline 3 will go high and the gates of the n-channel bit switch devices 4a and 4b will go high and the gates of the p-channel bit switch devices 5a and 5b will go low. This is in the direction to turn on the complementary bit switches. Bit lines 6 and 7 and input/output (I/O) lines 8 and 9 are initially high. Assume bit line 6 (Image Omitted) is discharged by the selected cell 10.

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CMOS Self-Timed Sense Amplifier Circuit

A sense amplifier for static random-access memories using complementary metal oxide semiconductors and timed from the accessed wordline provides reliable, high-speed operation over wide parameter variations using a setting signal with slow and fast setting slopes and decoupling devices. In Fig. 1, assume row decoder 1 and column decoder 2 are selected for a read. Wordline 3 will go high and the gates of the n-channel bit switch devices 4a and 4b will go high and the gates of the p-channel bit switch devices 5a and 5b will go low. This is in the direction to turn on the complementary bit switches. Bit lines 6 and 7 and input/output (I/O) lines 8 and 9 are initially high. Assume bit line 6

(Image Omitted)

is discharged by the selected cell 10. The n-channel bit switch 4a does not turn on until bit line 6 discharges by at least a threshold voltage. However, the p- channel bit switch 5a (and 5b) has a large voltage across it at the start of a cycle and forms a relatively low resistance connection to the I/O lines. The differential voltage buildup across bit line pairs 6 and 7 is propagated through the selected complementary bit switch onto the I/O lines and through devices 18 to sense amplifier 12. The n-channel bit switches (4a or 4b) are necessary for a write operation to discharge a selected bit line to ground. During a write operation with I/O line 8 or 9 set low, the p-channel bit switches 5a and 5b cut off because of their threshold voltage and cannot discharge the bit line to a low level; hence, complementary bit switches are necessary. As a selected wordline rises and turns on its memory cell 10, it also causes its set signal generator 11 to be activated. Set signal generator 11 is connected to both lin...