Browse Prior Art Database

Complementary Vertical Bipolar Transistors

IP.com Disclosure Number: IPCOM000035019D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Chen, TC: AUTHOR [+6]

Abstract

Disclosed is a high performance vertical pnp device structure suitable for complementary bipolar (npn and pnp) process integration. It is accomplished by placing a buried highly conductive layer very close to the active device region for reducing collector resistance. A buried highly conductive subcollector layer (1) for pnp is formed during the shallow trench process. Either silicide (1) shown in Fig. 1A or heavily doped p+- layer (1) using selective-epi process shown in Fig. 1B is formed after shallow trench etching. The highly conductive layer is then covered by oxide-refill as commonly done in the conventional shallow trench process. The rest of pnp process steps simply follows the "double-poly" npn process by changing the type of dopants accordingly.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Complementary Vertical Bipolar Transistors

Disclosed is a high performance vertical pnp device structure suitable for complementary bipolar (npn and pnp) process integration. It is accomplished by placing a buried highly conductive layer very close to the active device region for reducing collector resistance. A buried highly conductive subcollector layer (1) for pnp is formed during the shallow trench process. Either silicide (1) shown in Fig. 1A or heavily doped p+- layer (1) using selective-epi process shown in Fig. 1B is formed after shallow trench etching. The highly conductive layer is then covered by oxide-refill as commonly done in the conventional shallow trench process. The rest of pnp process steps simply follows the "double-poly" npn process by changing the type of dopants accordingly.

(Image Omitted)

The high performance vertical pnp transistor is achieved through a buried highly conductive subcollector layer surrounding the active device area and a dense device layout to reduce parasitics. The npn part (shown in Fig. 1C) by itself is very similar to U.S. Patent 4,446,476. This pnp structure permits the integration of vertical pnp and vertical npn on standard non-patterned n-/n+ epitaxy wafers.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]