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Method of Implementing a UART Using Digital Signal Processing Techniques

IP.com Disclosure Number: IPCOM000035031D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Locke, ME: AUTHOR

Abstract

Traditional UART (universal asynchronous receiver transmitter) receivers perform rapid binary (one bit) sampling of an input data stream. The sampling rate is typically 10-20X the actual bit rate. The resultant sample stream is examined to extract data. Oversampling is required in order to get accurate start bit location estimates. The accuracy of the start bit location estimate has a substantial influence on the error rate performance of a UART when the 0/1 timing is asymmetric. When a modem is designed using digital signal processing, this oversampling process can require an excessive amount of processing power. This method seeks to reduce the processing power without reducing the performance of the UART.

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Method of Implementing a UART Using Digital Signal Processing Techniques

Traditional UART (universal asynchronous receiver transmitter) receivers perform rapid binary (one bit) sampling of an input data stream. The sampling rate is typically 10-20X the actual bit rate. The resultant sample stream is examined to extract data. Oversampling is required in order to get accurate start bit location estimates. The accuracy of the start bit location estimate has a substantial influence on the error rate performance of a UART when the 0/1 timing is asymmetric. When a modem is designed using digital signal processing, this oversampling process can require an excessive amount of processing power. This method seeks to reduce the processing power without reducing the performance of the UART. In order to implement this UART the detector algorithm is first redesigned to generate a signal level rather than a 1-bit sample stream (see the figure). This signal level is designed to be positive to represent a 0 and negative to represent a 1. In this implementation, the detector output is oversampled by 5X. When the transition for a start bit is detected (transition from 0 to 1), a sample is interpolated between the last positive sample and the current negative sample. If this interpolated sample is negative, then the start bit is considered to begin 1/2 sample earlier than the sampling time. The remainder of the data byte is determined based on this point, interpolating samples as ne...