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Signal Processor Hardware Architecture for Optimum Instruction Efficiency

IP.com Disclosure Number: IPCOM000035034D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Locke, ME: AUTHOR

Abstract

In the design of digital signal processor hardware there are 3 competing design criterion: 1-instruction speed, 2-instruction complexity, 3-instruction word length. A given processing task may be accomplished with fewer complex instructions but as the expense of instruction speed. Long word lengths require much expensive RAM and decode logic and are therefore more expensive to implement even though the parallelism thus achieved will allow both high speed and high instruction complexity. The architecture presented in the figure represents a near optimum configuration for digital signal processing. A Harvard architecture is used to make optimum use of bus accesses and to allow different data and instruction word sizes.

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Signal Processor Hardware Architecture for Optimum Instruction Efficiency

In the design of digital signal processor hardware there are 3 competing design criterion: 1-instruction speed, 2-instruction complexity, 3-instruction word length. A given processing task may be accomplished with fewer complex instructions but as the expense of instruction speed. Long word lengths require much expensive RAM and decode logic and are therefore more expensive to implement even though the parallelism thus achieved will allow both high speed and high instruction complexity. The architecture presented in the figure represents a near optimum configuration for digital signal processing. A Harvard architecture is used to make optimum use of bus accesses and to allow different data and instruction word sizes. Since the most common operation in digital signal processing is convolution (sum of products), a multiplier/ accumulator is provided. Each multiply usually requires 2 operands, so 2 data RAMs and 2 data buses are incorporated. The result of a multiply has twice as many bits as the inputs, so the result can be stored in one bus cycle using both data RAMs simultaneously as a single RAM. A separate ALU is provided so that more complex operations, such as "butterflies", can be executed efficiently. The ALU is designed to perform accumulation or Winograd butterflies (sum and difference) efficiently. The results of an operation may be loaded into the accumu lator and output register or...