Browse Prior Art Database

Shared Addressing Unit for Jump State Controller and Multiple Rams With Minimal Complexity Control Logic

IP.com Disclosure Number: IPCOM000035036D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Locke, ME: AUTHOR

Abstract

The design of digital signal processors with multiple RAMs/buses involves a tradeoff between instruction complexity, instruction length, and instruction efficiency. A large number of index registers for each RAM, each with an immediate offset provides optimum instruction efficiency. Such a solution requires a long instruction word to control the index registers and provide the immediate offsets. Substantial hardware is required to implement the index registers. This article is for an architecture which achieves near optimum instruction efficiency for digital signal processing tasks with substantially reduced instruction complexity as compared to the optimum implementation. The figure depicts the address generator architecture.

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Shared Addressing Unit for Jump State Controller and Multiple Rams With Minimal Complexity Control Logic

The design of digital signal processors with multiple RAMs/buses involves a tradeoff between instruction complexity, instruction length, and instruction efficiency. A large number of index registers for each RAM, each with an immediate offset provides optimum instruction efficiency. Such a solution requires a long instruction word to control the index registers and provide the immediate offsets. Substantial hardware is required to implement the index registers. This article is for an architecture which achieves near optimum instruction efficiency for digital signal processing tasks with substantially reduced instruction complexity as compared to the optimum implementation. The figure depicts the address generator architecture. Only 1 immediate field, one adder, N+1 index register (implemented as counters), and miscellaneous buffers are required (N is the number of RAMs). One control bit per counter (increment, nop), one control bit per buffer (enable buffer, enable counter), and address width immediate data are required from the control store. In most signal processing applications, sequences for sum of product calculations are done. Typically, one of the multipliers is a constant and read from a table in RAM. It is therefore generally possible to arrange the RAM table so that the constants are used sequentially (can be indexed by a counter). The other multiplier is typically data and often is needed in non-sequential order. The final result of each calculation is typically stored sequentially. This architecture allo...