Browse Prior Art Database

Interprocess Hardware Interference Detection

IP.com Disclosure Number: IPCOM000035045D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 38K

Publishing Venue

IBM

Related People

Marquart, DW: AUTHOR

Abstract

A method solving a class of problems where there are two processes updating a resource, one interruptible (non-atomic) and the other non- interruptible (atomic), is described. If two processes update the information in the same hardware resource (such as a register), there is a possibility that they will interfere with each other and corrupt the information. This is avoidable if both processes update the information in an uninterruptible manner, but requires more work if one process is interruptible and the other is not. A hardware process may be uninterruptible manner (atomic), while software may be interruptible (non-atomic) by the hardware process.

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Interprocess Hardware Interference Detection

A method solving a class of problems where there are two processes updating a resource, one interruptible (non-atomic) and the other non- interruptible (atomic), is described. If two processes update the information in the same hardware resource (such as a register), there is a possibility that they will interfere with each other and corrupt the information. This is avoidable if both processes update the information in an uninterruptible manner, but requires more work if one process is interruptible and the other is not. A hardware process may be uninterruptible manner (atomic), while software may be interruptible (non-atomic) by the hardware process. This method may be applied in situations with the following characteristics: * there are two sources of updates to a piece of hardware

(such as a register; for example, the days counter)

* one source of updates is atomic and always performs

predictable manipulations to the hardware.

Predictable manipulations are, for example, incrementing, setting a bit or bits, resetting a bit or bits, or

incrementing and possibly resetting a counter (such as

the days counter).

"Atomic" means that the process is uninterruptible - it

always completes before anything else may use the piece

of hardware.

* One source of updates to the piece of hardware is not

atomic.

* There is sufficient time between atomic updates to the

hardware to allow the non-atomic process to detect and

correct interference. If there is not enough time

guaranteed for correction, but there is enough time for

detection, then repeated application of this method will

eventually allow for correction. This process provides a way of avoiding complicated hardware that makes both processes that update a piece of hardware atomic with respect to the update. The following features are involved in the program.

* a piece of hardware, such as a register, that may contain

information

* an atomic (uninterruptible) process that updates the

information in the hardware

* a non-atomic (interruptible) process that updates the

information in the hardware

* the condition that both the atomic and the non-atomic

process may attempt to update the information at the same

time

* the requirement that the non-atomic process detect

interference from the atomic process and correct the

1

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results

* a "check bit" that is

- set when the non-atomic process reads the information

prior to updating the information

- reset when the atomic process updates the information

The mechanisms for doing the setting and resetting are

included in the process. See the figure.

* the property of this arrangement of features that a

simple

algorithm allows the non-atomic process to determine

whether an update resulted in an invalid value

* The ability to detect and correct interference The non-atomic process may not read from the target register (other than as specified in the algorithm) until the following algorithm is complete....