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Structured 64-Bit Leading Zero Encoder

IP.com Disclosure Number: IPCOM000035056D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 108K

Publishing Venue

IBM

Related People

Desrosiers, B: AUTHOR [+2]

Abstract

The principle of this circuit lies on the separation of the 64-bit number into 8 groups of 8 bits each. As shown on the joined schematic, the counting of the leading zero (LZ) in each group is performed in the upper half page and, the counting of the number of groups at zero is performed in the lower half page. The structure used for the groups is exactly the same as the structure used for the bits in a group. The group of NOR gates operates as follows: - The first left column counts the number of leading zeros in group 7. If there are between 0 and 7 leading zeros, only the NOR output corresponding to the number of LZs would be active (output 70 to 77). - The other columns count the leading zeros in group 0 to group 6 in the same manner.

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Structured 64-Bit Leading Zero Encoder

The principle of this circuit lies on the separation of the 64-bit number into 8 groups of 8 bits each. As shown on the joined schematic, the counting of the leading zero (LZ) in each group is performed in the upper half page and, the counting of the number of groups at zero is performed in the lower half page. The structure used for the groups is exactly the same as the structure used for the bits in a group. The group of NOR gates operates as follows: - The first left column counts the number of leading zeros in group 7. If there are between 0 and 7 leading zeros, only the NOR output corresponding to the number of LZs would be active (output 70 to 77). - The other columns count the leading zeros in group 0 to group 6 in the same manner. The first digit of a NOR output indicates the group number, and the second digit indicates the number of leading zeros in the group. As an example, consider the number given in Fig. 1. As shown in Fig. 2, only the output 23 of gate A in the upper half is activated.

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The controls coming from the lower half inhibit gates B and C which would otherwise be active. In the lower half the output 40 of gate D is active (low). It indicates 5 groups are at zero. The output 3 of gate E which inputs are all the third output of each group is also active (low). The right shift amount 40 (output 40 on BUS m) + 3 (output 3 on bus n) = 43 has been generated. A CMOS implementation leads to 3 le...