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SCSI RESELECTION PHASE DETECTOR

IP.com Disclosure Number: IPCOM000035057D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 6 page(s) / 92K

Publishing Venue

IBM

Related People

Christianson, MD: AUTHOR

Abstract

The SCSI (Small Computer System Interface) specification requires that a target on the SCSI bus, which is trying to reselect an initiator, arbitrate and win control of the bus before entering the Reselection Phase. Once in the Reselection Phase, the target will release busy after having activated select, I/O and the initiator's ID bit on the data bus. The initiator is to detect this condition for at least 400 ns before responding to the target by activating busy. (Image Omitted) The Reselection Phase will begin with the device, already driving select and I/O true, driving the initiator's ID bit and its own ID bit on the data bus at least 90 ns before it releases busy (1 - see Fig. 1). The initiator must determine if it is the intended target of the reselection attempt by detecting its ID bit active on the data bus.

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SCSI RESELECTION PHASE DETECTOR

The SCSI (Small Computer System Interface) specification requires that a target on the SCSI bus, which is trying to reselect an initiator, arbitrate and win control of the bus before entering the Reselection Phase. Once in the Reselection Phase, the target will release busy after having activated select, I/O and the initiator's ID bit on the data bus. The initiator is to detect this condition for at least 400 ns before responding to the target by activating busy.

(Image Omitted)

The Reselection Phase will begin with the device, already driving select and I/O true, driving the initiator's ID bit and its own ID bit on the data bus at least 90 ns before it releases busy (1 - see Fig. 1). The initiator must determine if it is the intended target of the reselection attempt by detecting its ID bit active on the data bus. The initiator will have an internal three-bit software-controlled register (Idreg(0:2)) in which its SCSI ID is stored. It must match its assigned ID with the corresponding bit on the SCSI data bus. One of the operators Sid0 through Sid7 will be active (a decode of the three-bit ID register) and will indicate to which bit the initiator's ID corresponds. If the initiator's ID bit is active on the data bus, one of the operators Rs10 through Rs17 will be active. These seven operators are 'ORed' together to generate Rslind, which indicates the initiator has been targeted for the reselection.

(Image Omitted)

Operator Rslphs is the product of the four signals which need to be stable for at least 400 ns: -busy, select, I/O and Rslind.

Rslphs feeds the data input to latch Cntr8a L1, the first bit of a three-bit serial counter used to count the 400 ns detection period. Cntr8a, Cntr8b, and Cntr8c are all clocked by Cclk (for the L1's) and Bc1k (for the L2's), which are non-overlapping LSSD clocks with a 25% duty cycle and a period of 100 ns. The time from when Cntr8a L2 becomes set until Cntr8b L2 clears is the 400 ns window (2 - see Fig.
1) during which latch Cntr8d is used to detect any change of state in Rslphs, down to the smallest of glitches. Cntr8d, with its Cc1k tied active and a normal 100 ns oscillating Bc1k, will become set immediately upon Rslphs switching to a b'0' (see examples in Fig. 2 which depict busy glitching). This will cause latch Cntr8e to set on the following Cc1k and Bc1k pulses. Cntr8e will be active for only 100 ns and will reset SCSI RESELECTION PHASE DETECTOR - Continued Cntr8d. Cntr8d L2, also active for only 100 ns, will cause Cntr8a, Cntr8b and Cntr8c to reset. Once Cntr8d L2 has been reset, Cntr8a will become set again if Rs1phs is valid. 4, 5, and 6 (see Fig. 2) are examples of the logic detecting glitches on the busy signal during the detection window (busy is the most likely signal to glitch

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since select, I/O and the data bus are supposed to be stable before busy is released by the device). 7 depicts a glitch occurring before the window (before Cntr...