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"Special Case" Arithmetic Handling for IEEE Floating Point Hardware

IP.com Disclosure Number: IPCOM000035061D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Brown, JD: AUTHOR

Abstract

A hardware implementation of the IEEE floating point specification must be able to handle all numeric types defined in the standard. The algorithms used to calculate numeric results fail on many of the numeric types. The presence of these "special case numbers" are detected and the correct result is generated for each case. A floating point processor has a number of sequencers that control the arithmetic processing. Each sequencer is designed specifically for a particular arithmetic function. For example, the multiply sequencer (MLTSEQ) handles all control aspects of the multiply calculation. There is one additional arithmetic sequencer referred to as the Special Case Sequencer. Its job is to process all occurrences of operand pairs where one or both of the operands is not a +/- real number.

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"Special Case" Arithmetic Handling for IEEE Floating Point Hardware

A hardware implementation of the IEEE floating point specification must be able to handle all numeric types defined in the standard. The algorithms used to calculate numeric results fail on many of the numeric types. The presence of these "special case numbers" are detected and the correct result is generated for each case. A floating point processor has a number of sequencers that control the arithmetic processing. Each sequencer is designed specifically for a particular arithmetic function. For example, the multiply sequencer (MLTSEQ) handles all control aspects of the multiply calculation. There is one additional arithmetic sequencer referred to as the Special Case Sequencer. Its job is to process all occurrences of operand pairs where one or both of the operands is not a +/- real number. The Special Case Sequencer (SPCSEQ) seizes control from the selected arithmetic sequencer using a signal called SPCASEIN which indicates that a Special Case Operand was detected. The SPCSEQ then uses the R2 FPU dataflow to create the correct result. A floating point processor loads the final result of all arithmetic operations into FAREG. This result may be stored to the internal array or stored to main store. It is also possible to leave the result in FAREG for use as Operand 2 on the next arithmetic operation. The processor includes logic necessary to detect the occurrence of a special case operand as the result of the arithmetic.

This allows the use of FAREG as a floating point accumulator. Two registers store the type of the operands loaded into the working registers FA and FB. They are FASTAT and FBSTAT, respectively. The control signals generated from FASTAT and FBSTAT are used by the SPCSEQ to control the FPU dataflow to create the result. The SPCSEQ maps the listed control signals (see Fig. 1) into the following signals which indicate where the result that is to be loaded into FA should come from. RSLTFA - This signal indicates that the result

will be made from the operand loaded into FA.

RSLTFB - This signal indicates that the result

will be made from the operand loaded into FB.

RSLTCMP - This signal indicates that the result

will be determined by comparing the fraction in FB

with the fraction in FA. The larger of the two

will be the result fraction field and loaded into

FA.

RSLTZERO - A result of zero must be loaded into

FA.

RSLTINF - A result of Infinity must be loaded into

FA.

RLSTFNAN A result of Fixed NAN must be loaded into

FA. A FNAN is a masked NAN with the fraction

field all B'...