Browse Prior Art Database

Dynamic Pneucs for Chips

IP.com Disclosure Number: IPCOM000035064D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Merkel, DA: AUTHOR

Abstract

Gate array (GA) chip images and standard cell (SC) chip images each have their own advantages. GA chip images have shorter manufacturing turn-around time (TAT), and SC chip designs can contain a large variety of high density circuits. This proposal is an attempt to develop a methodology to create chip images that contain all of the advantages of both GA and SC chips. As chip densities increase, the ability to put a varied collection of macros on a chip make SC chips more attractive. At the same time, manufacturing schedules are such that GA chips should be used. This proposal suggests a methodology that future chip technology development should consider to gain the advantages of both SC and GA chip approaches. Fig. 1 shows the varied configurations of chips that system designers will require.

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Dynamic Pneucs for Chips

Gate array (GA) chip images and standard cell (SC) chip images each have their own advantages. GA chip images have shorter manufacturing turn-around time (TAT), and SC chip designs can contain a large variety of high density circuits. This proposal is an attempt to develop a methodology to create chip images that contain all of the advantages of both GA and SC chips. As chip densities increase, the ability to put a varied collection of macros on a chip make SC chips more attractive. At the same time, manufacturing schedules are such that GA chips should be used. This proposal suggests a methodology that future chip technology development should consider to gain the advantages of both SC and GA chip approaches. Fig. 1 shows the varied configurations of chips that system designers will require. SC chips can contain a variety of macros but unused circuit locations contain no circuit devices. GA chips are an mxn array of basic logic circuits. In these chips, unused circuits locations contain circuits which can be used in future chip design changes with only back end of line (BEOL) wire data changes only. In this proposal, the early design of a chip proceeds as though the chip is going to be a SC chip. This is shown in design step 1 of Fig. 2. Iterations may occur at this point until a certain confidence is reached. It is at this point that the chip front end of line (FEOL) data may be released. A dynamic pneuc, a rule which points to other ru...