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High Speed Incrementer

IP.com Disclosure Number: IPCOM000035075D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR

Abstract

An incrementer with selector logic that chooses one of two generated values for each bit depending on the state of a carry signal into a sub-section of bits achieves high speed while maintaining small area occupancy by the incrementer.

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High Speed Incrementer

An incrementer with selector logic that chooses one of two generated values for each bit depending on the state of a carry signal into a sub-section of bits achieves high speed while maintaining small area occupancy by the incrementer.

The incrementer is organized in 4 bit sections made up of a three bit section shown in Fig. 1 plus a one bit sub-section as shown in Fig. 2A for a first 4 bit section. A second 4 bit section is comprised of the 3 bit section (Fig. (1) plus a one bit sub-section, as shown in Fig. 2B. This sequence of 4 bit sections, alternately using first the circuit of Fig. 2A and then the circuit of Fig. 2B for the fourth bit, may be continued to build an incrementer of any length.

Each bit circuit of the 3 bit incrementer section of Fig. 1 creates an incremented value. A selector circuit 4, 14, or 24 selects the input bit IN1, IN2, IN3 or the incremented value depending on a carry input value on line C1. OR gate 8 and NAND gate 10 comprise an OR-AND-INVERT function. AND gate 20 and NOR gate 22 form an AND-OR- INVERT function. Carry output on line C2 feeds the fourth bit circuit, either line C3 in Fig. 2A or line C4 in Fig. 2B.

Interaction of the circuits of Fig. 1, Fig. 2A and Fig. 2B is as follows. A carry ripples out of NAND gate 6, through NOR gate 18, out of line C2, and into line C3 of Fig. 2A to NAND gate 26. The carry signal is not restored between bits. CARRY NOT comes out of NAND 6 to NOR 18 and input IN1 goes to...