Browse Prior Art Database

NMOS Control Circuit for a CMOS Three-State Driver

IP.com Disclosure Number: IPCOM000035078D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Piro, RA: AUTHOR

Abstract

A circuit is shown which utilizes a CMOS three-state output driver stage controlled by NMOS input stages to take advantage of the low power attributes of the CMOS driver while accepting input signals from other NMOS circuits.

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NMOS Control Circuit for a CMOS Three-State Driver

A circuit is shown which utilizes a CMOS three-state output driver stage controlled by NMOS input stages to take advantage of the low power attributes of the CMOS driver while accepting input signals from other NMOS circuits.

Referring to the figure, the circuit combines redundant logic functions into a single two-legged logic tree and performs a multiplexing function by passing either data input (D1 or D2) to the output node or putting the output in a high impedance state, with both devices T21 and T22 off. Devices T1-T16 make up the controlling NMOS logic, and devices T17-T20 are two CMOS buffer/inverters which drive output devices T21 and T22.

Input signals from NMOS logic circuits using push-pull buffered outputs feed inputs D1, D2, E1, E2, C1 and C2. While the up level of the input signals is not sufficient to drive a CMOS circuit directly, the NMOS logic is designed to provide appropriate signal levels at nodes E and F capable of driving the CMOS buffers.

In addition to acting as an interface between the low level input signals and the CMOS drivers, the NMOS logic stage also saves space when compared with its equivalent function implemented in CMOS logic. If the logic function performed by devices T5-T16 were implemented in CMOS, as many p-channel devices would be required to pull up nodes E and F as are used to pull these nodes down. A substantial saving in area is realized by using two depletion loads (T5 and T6). Also, nodes E and F are never low together, minimizing the power loss due to using NMOS circuits.

Inputs E1, C...