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General Adapter Architecture Applied to an ESDI File Controller

IP.com Disclosure Number: IPCOM000035079D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 115K

Publishing Venue

IBM

Related People

Lochner, DL: AUTHOR

Abstract

A general architecture is described which allows multiple device adapters to share a common memory space in a Personal Computer or similar system. The concepts are illustrated by a description of an ESDI file controller card which applies the architecture.

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General Adapter Architecture Applied to an ESDI File Controller

A general architecture is described which allows multiple device adapters to share a common memory space in a Personal Computer or similar system. The concepts are illustrated by a description of an ESDI file controller card which applies the architecture.

Multiple devices, performing similar or different functions, can share memory space in a computer system if those devices follow a common convention for usage of memory addresses. Fig. 1 represents a possible arrangement of memory space. The "Shared Area" 1 is a range of addresses to be shared by all such devices, one device at a time. "Control Area" 2 is another range of addresses in which specific addresses are assigned to specific devices. Within the Control Area, each set of addresses which apply to a single device are designated as a "Control Block" 3.

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Addresses within a Control Block allow the controlling computer to access some parts of each device at all times. Certain of these addresses may be registers, with bits which can gate some other part of the device into the shared area of the memory space.

In Fig. 1, the "Shared Memory" area has multiple columns (Case 1 through Case "m"). Each column represents different memories or other circuits of one device which might be gated into that memory region at a specific time, by actions taken on the Control Block for that device. Case 1 might represent an idle condition, in which none of the devices have components which are selected to be in the Shared Area. The devices themselves could either be idle, or busy performing their assigned task with no intervention required by the host computer. Subsequent Cases represent times when a part of one device is gated into the Shared Area for transfer of data or control information between the device and the host computer.

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A conceptual block diagram of hardware which might implement this architecture is shown in Fig. 2. Key components are: The Host Bus 4 represents the address, data, and control signals by which the host computer communicates with the Control Block of the device. Control Logic 5 implements the portion of the Control Block which gates parts of the device into the Shared Area of memory, and enables operations by an optional microprocessor 6. The architecture allows, but does not require, a microprocessor 6 or other type of controller to execute certain functions independently of the host computer. The Local Bus 7 interconnects the devices which may operate independently, or which are selectively gated into the shared area of the host computer's memory. Buffers 8 and 9 allow components on the Local bus to be accessed by either the local controller, or by the host computer.

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Architectural concepts are shown by example of an adapter card designed to attach an ESDI disk drive to a Personal Computer. Up to 6 of these cards can be simultaneously installed...