Browse Prior Art Database

SPD I/O Bus Interactive Test System

IP.com Disclosure Number: IPCOM000035091D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Calvert, RS: AUTHOR [+3]

Abstract

A controlled, repeatable means of initiating a wide variety of bus operations, detecting and injecting bus errors, and monitoring activity on an IBM SPD I/O bus is provided in the following.

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SPD I/O Bus Interactive Test System

A controlled, repeatable means of initiating a wide variety of bus operations, detecting and injecting bus errors, and monitoring activity on an IBM SPD I/O bus is provided in the following.

The SPD bus interactive test system (BITS) runs on the SPD I/0 Bus Test Vehicle (BTV) hardware (Fig. 1). The BTV consists of a personal computer (PC), a TESLA I/O Processor (IOP) card, and an associated error injection/error detection (EI/ED) I/0 adapter (IOA) card. The PC communicates to the TESLA IOP via a general-purpose interface bus (GPIB) [IEEE-488].

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The TESLA IOP controls the EI/ED card and accepts status from it via the IOA bus. The TESLA IOP contains a microprocessor, memory, and an interface that allows it to communicate over the SPD I/O bus. BITS microcode runs inside the TESLA IOP, and can also access registers inside the EI/ED card.

The EI/ED card contains circuitry that allows it to detect errors and inject errors on the SPD I/O bus. It can accept commands and parameters from the TESLA IOP. It can issue an interrupt to the TESLA when error detection or injection status is available.

The TESLA portion of BITS is part of the BTV RAM Code. The PC portion of BITS is written in C and compiled with the IBM C Compiler. BITS software is part of the Operator Console Program (OCP). The IBM PC GPIB Adapter Programming Support Routines is used in the PC portion of BITS to communicate via the GPIB bus. Full Screen Executive (FSX/PC) is used to implement PC screens. The TESLA portion of BITS is written in PL.8, and compiled with the PL.8 Compiler. The TESLA por tion uses the BTV ROS Code. The TESLA portion also uses the X-Series Control Program (XCP), which is part of the IBM 6030 Communications Adapter microcode.

BITS consists of two separate programs that work together. The PC portion runs on the IBM PC, PC/XT, PC/AT, PS/2, or compatible PCs under the DOS operating system. The PC portion of BITS is a functional component of OCP, a program that contains the user interface for the SPD I/0 BTV. The TESLA portion runs in the TESLA IOP under the XCP operating system. BITS software structure is shown in Fig. 2.

The TESLA IOP portion of BITS is a functional component of the BTV RAM code. The BTV RAM code, together with the BTV ROS code, issues and accepts SPD I/O Bus operations. The BTV RAM code also controls and services the EI/ED hardware. Finally, the BTV RAM code accepts and responds to commands from the PC via the GPIB interface.

BITS alleviates the need for writing special programs to perform SPD I/0 Bus level testing from an IOP. Instead, the BITS Operation List Definition screen allows the user to create a customized list of virtually any sequence of bus operations. This operation list can be saved in a file for future use.

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The operation list can be as simple as a single unit me...