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Print DATA Generation Logic for Dot Matrix Printer

IP.com Disclosure Number: IPCOM000035124D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Hisano, T: AUTHOR [+2]

Abstract

A data generation logic for a dot matrix printer is provided that works independently from the printer controller and simplifies dot image handling. It is suitable for those printers which have complicated pin alignment, such as the multi-column line printer or diamond shaped alignment serial printer. To pick up a desired data bit from the line image buffer, this logic uses a memory circuit as an address translator for image buffer to be addressed with respect to the head carrier position and dot pin number. This logic is applicable to any type of dot pin alignment with some minor modification of circuit and initialization of memory contents.

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Print DATA Generation Logic for Dot Matrix Printer

A data generation logic for a dot matrix printer is provided that works independently from the printer controller and simplifies dot image handling. It is suitable for those printers which have complicated pin alignment, such as the multi-column line printer or diamond shaped alignment serial printer. To pick up a desired data bit from the line image buffer, this logic uses a memory circuit as an address translator for image buffer to be addressed with respect to the head carrier position and dot pin number. This logic is applicable to any type of dot pin alignment with some minor modification of circuit and initialization of memory contents.

Dot matrix printers perform printing by constructing a character with certain numbers of printed dot matrix. Normally, these printers generate a line image buffer before printing one line, in which each data bit in the buffer corresponds to the print data image. At the printing, they must make the data bits match to the alignment of each pin.

This logic is a method to pick up the data bit from the line image buffer and to construct the print data bits for each pin. To access the data bit out of the buffer for each pin, a memory circuit is used as an address translator as a combination logic. The specified data bit is selected by a data selector from the accessed data.

The figure shows the logic structure of this method. The BASE COUNTER is an n-bit counter which indicates th...