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CIRCUIT CONCEPT FOR WRITE-FLUSH OPERATION IN SRAMs

IP.com Disclosure Number: IPCOM000035129D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 159K

Publishing Venue

IBM

Related People

Chin, W: AUTHOR [+4]

Abstract

A method has been proposed to make it possible to use high-speed random patterns at the module self-testing step for modules with array chips and logic chips used in semiconductor devices. The proposed circuit for flush operations makes it possible to perform random pattern testing without any adverse effect on normal array operation. (Image Omitted)

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CIRCUIT CONCEPT FOR WRITE-FLUSH OPERATION IN SRAMs

A method has been proposed to make it possible to use high-speed random patterns at the module self-testing step for modules with array chips and logic chips used in semiconductor devices. The proposed circuit for flush operations makes it possible to perform random pattern testing without any adverse effect on normal array operation.

(Image Omitted)

To enhance test coverage and reduce test analysis time, a high- speed fault simulator capable of simulating the effects of random pattern tests applied at the chip or multiple chip module is required.

To make the operation possible, a flush-circuit concept has been implemented which, after applying an ON-signal changes the array operation by
(1) having the flush operation independent of the external clock signal, (2) inhibiting the write operation during flush, (3) flushing the data-in of the selected subarray to the output driver if the read-byte address matches the write-byte address, and (4) feeding the data stored in the selected subarray to the data-out driver if the addresses do not match.

During a normal write or flush operation the left or right bit line is pulled to an UP-level. However, information in the cells must not be changed during flush; therefore, both the select (ILW) and write (IUW) currents of the selected subarray should either be turned off or gated away from the word line.

(Image Omitted)

Fig. 1 shows one of the four subarrays. The lower word lines (LWL 0...63) and upper word lines (UWL 0...63) are connected to separate current sources (ILW and IUW) via transistors TLW and TUW. Selecting a word line requires an UP-level at the corresponding word-decoder line (WDL 0...63). During WRITE, both TLW and TUW are conducting, pulling down both the lower and upper word line. During READ transistor TU has been added so the UWL is not pulled down. Its base potential is controlled indirectly by the state of the write-byte-select (WBS) line. As long as WBS is unselected (e.g., "READ") the potential of RBW is 400 mV higher than that of the WDL, and TLW is non-conducting. To prevent a change in cell data required for the flush operation both word line drivers TLW and TUW have to be kept non-conducting. This is achieved by adding transistor TU and switching its base WBW together with the base RBW of TL to ground.

The level of RBW and WBW is set by the write-flush-control (WFC) circuit of Fig. 2, with there being one WFC circuit for each of the four subarrays. During flush, only the WFC circuit of the subarray selected by the WBS data has a selected DOWN-level at its input FLS. Outputs RBW and WBW of th...