Browse Prior Art Database

Five-Volt Dcsl-To-Ttl Driver With Inhibit

IP.com Disclosure Number: IPCOM000035131D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Mullgrav, AL: AUTHOR

Abstract

This article describes a fast low power output driver-buffer that converts DCSL (differential current switch logic) internal signal levels to TTL (transistor-transistor logic) off-chip levels as a means of interfacing DCS chips with other technologies, e.g., CMOS and TTL.

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Five-Volt Dcsl-To-Ttl Driver With Inhibit

This article describes a fast low power output driver-buffer that converts DCSL (differential current switch logic) internal signal levels to TTL (transistor- transistor logic) off-chip levels as a means of interfacing DCS chips with other technologies, e.g., CMOS and TTL.

The CSL (current switch logic)/TTL driver with inhibit, shown in the figure, employs a 2 um device technology with three layers of metal. The circuit illustrated uses a differential input stage to control a push-pull output stage, with the Cavaliere clamp used to limit the circuit uplevel. Nominal delay is 4.5 ns at a power dissipation of 21 mw. Delay variation is less than +/-25% within temperature, process and power supply range limits.

A unique feature of the driver circuit illustrated in the figure is the way in which the signal applied to inputs IN is transferred to the output [0]. Existing approaches typically use the gain developed across the collectors (at the input stage) to drive the output while the disclosed circuit uses gain developed in current mirrors (in the emitters of the input stage) for this purpose. The differential input swings from the power supply (Vcc) value, to ~ -0.5 V below Vcc. Although lower voltages, e.g. emitter-follower outputs, could have been used to drive the inputs (IN1 and IN2), circuit operation depends on the differential nature of the input signal rather than voltage levels. This is shown as follows:

Assuming a rising input transition at IN1, and a falling transition at [IN2], transistors T3 and T6 form a current mirror such that the current through resistor R4 equals the current through R2. Similarly, transistors T5 and T2 make the current passing through resistor R1 equal to that through resistor R3. If the input signal at IN1 is increased by the voltage WV, the increase in current through R2 is WV/R2 and the resulting increase in voltage drop across R4 is expressed by WV/R2 x R4 = WV

If the input signal at IN2 moves downward by an amount WV at the same time that IN1 moves upward, the node 7 must move downward by the amount WV, and node 8 must move downward by 2 x WV. The voltage at node 2 would also move upward by 2 x WV if it were not clamped by the base-emitter volta...