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Implementation of an Over-Writing ECL Logic

IP.com Disclosure Number: IPCOM000035136D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Chuang, KCT: AUTHOR [+2]

Abstract

Disclosed is a new approach to implement an ECL logic function in which at least one of the inputs is an over-writing control, i.e., when an input causes the logic output to be at either a logical 1 or 0, irrespective of the other inputs. The new approach, in general, will save power, require less space, or improve speed or a combination of these, when compared with other known approaches when only non-inverted inputs are available. This is particularly useful in a VLSI environment, where similiar functional blocks may be encountered hundreds of times.

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Implementation of an Over-Writing ECL Logic

Disclosed is a new approach to implement an ECL logic function in which at least one of the inputs is an over-writing control, i.e., when an input causes the logic output to be at either a logical 1 or 0, irrespective of the other inputs. The new approach, in general, will save power, require less space, or improve speed or a combination of these, when compared with other known approaches when only non-inverted inputs are available. This is particularly useful in a VLSI environment, where similiar functional blocks may be encountered hundreds of times.

The concept is described via a two-input logic function, Z = AB. In this case, A is the over-writing control which, when active, forces Z to a logical 0. The new implementation of this function is depicted in Fig. 1 (emitter-followers are not shown). The voltage levels of input B is at the normal ECL levels. The logical 0 voltage level of input A is at the voltage reference level (VREF), but the logical 1 voltage level is raised (hence labelled as A+). The raised level in A is the key to the over-writing control as it is higher than the high- level of B and therefore determines the logic output irrespective of B. The amount raised is the same as the difference between the high-level of B and VREF. For example, it is 300 mV, for a 600 mV ECL swing. In

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this implementation, the logic delay is one gate-delay and power consumption is one gate-power. Note that t...