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Eliminating Radiated Sources for Emissions for Microprocessors With Multiplexed Signals

IP.com Disclosure Number: IPCOM000035139D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Hardin, KB: AUTHOR

Abstract

When an electronic module buffers or latches the address/data bus of an Intel 8088, 80188, 8086, or 80186 microprocessor, the output produced by the buffer or latch creates radiated emissions on the output address or data bus resulting from the microprocessor having invalid periods between the address and the following data cycle or between the data cycle and the following address of the next cycle. These invalid periods typically involve one or more changes of state. The consequent radiation is avoided by delaying when the addresses are changed and when the data is transmitted until the information is guaranteed valid.

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Eliminating Radiated Sources for Emissions for Microprocessors With Multiplexed Signals

When an electronic module buffers or latches the address/data bus of an Intel 8088, 80188, 8086, or 80186 microprocessor, the output produced by the buffer or latch creates radiated emissions on the output address or data bus resulting from the microprocessor having invalid periods between the address and the following data cycle or between the data cycle and the following address of the next cycle. These invalid periods typically involve one or more changes of state. The consequent radiation is avoided by delaying when the addresses are changed and when the data is transmitted until the information is guaranteed valid.

By responding during the invalid periods, the output of the buffers or latches have a frequency of at least twice the frequency of the data or addresses and can be as much as 255 or more times greater in frequency (for high order lines). The radiated emissions are directly proportional to the frequency so that even a doubling of the frequency creates a 6 dB increase in radiated noise.

(Image Omitted)

As shown in Fig. 1, the address on the address/data bus from the Intel 8088, 80188, 8086, and 80186 microprocessor is valid when the ALE (address latch enable) signal goes down. Gating address signals is discussed below.

The following data is invalid when WR (not write) goes down. The data on the address/data bus from the microprocessor is not guaranteed valid until CLK OUT (the clock signal) during T2 goes up. The transition period between when WR goes down and CLK OUT during T2 goes up can vary from 5 to 20 nanoseconds because of system tolerances. During this time, any invalid transitions would be amplified by an electronic module 1 (Fig. 2) such as a 74LS373, if the module 1 is gated on during this period.

(Image Omitted)

The WR and PCS (not peripheral chip select) signals have previously been supplied through an OR gate 2 and an inverter 3 directly to the input gate of the electronic module 1. Thus, the output of the inverter 3 is high only when WR and PCS are low, which was before the invalid period in such a system and invalid signals were amplified by the module 1.

In the system shown, however, until CLK OUT goes up, the electronic module 1 is prevented from being enabled during T2 (Fig. 1), by a D-type flip flop 4 (Fig. 2) connected between the output of the inverter 3 and the input gate of the electronic module...