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Dynamic Method of Ensuring the Delivery of a Distributed Oscillator Pair

IP.com Disclosure Number: IPCOM000035158D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Jones, L: AUTHOR [+3]

Abstract

In a particular processor design an entire logic chip was dedicated to generating, checking and distributing multiple copies of a set of clocks. Each of these sets of clocks then required only minimal repowering on the final logic chip. As VLSI designs have increased the number of circuits and latches placed on a single logic chip, and as machine cycle times become faster, performance demands the distribution of very precise free running oscillators to be used for generating clocks on the final logic chip. This on chip generation will enhance the base distribution system and allow for optimal repowering of the generated clocks. The integral nature of the free running oscillators in the clocking scheme requires that a check be performed to ensure that these oscillators are being received on the chip.

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Dynamic Method of Ensuring the Delivery of a Distributed Oscillator Pair

In a particular processor design an entire logic chip was dedicated to generating, checking and distributing multiple copies of a set of clocks. Each of these sets of clocks then required only minimal repowering on the final logic chip. As VLSI designs have increased the number of circuits and latches placed on a single logic chip, and as machine cycle times become faster, performance demands the distribution of very precise free running oscillators to be used for generating clocks on the final logic chip. This on chip generation will enhance the base distribution system and allow for optimal repowering of the generated clocks. The integral nature of the free running oscillators in the clocking scheme requires that a check be performed to ensure that these oscillators are being received on the chip. The following will describe a method for checking that two oscillators (one delayed in time from the other) are arriving on the logic chip. If one of the oscillators is stuck at a high or low level this circuitry will detect and post an error condition.

The technique is illustrated by the following example. The period of these oscillators is divided into four parts. Given these four points in time, it becomes possible to check that if period 1 is recorded, and at some later time period 4 is recorded, then period 2 or period 3 should also have been recorded. If this did not happen, an error has occurred. For this particular assignment of periods one through four, this error would correspond to the second oscillator being stuck low. By shifting the assignment of numbers to periods one position to the right (period 2 becomes period 1 and period 1 becomes period 4). this error would then corr...