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Method for Address Fault Detection

IP.com Disclosure Number: IPCOM000035164D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 161K

Publishing Venue

IBM

Related People

Chencinski, EW: AUTHOR [+2]

Abstract

A method of providing a quick and rigorous diagnostic test for addressing faults and individual stuck data bits in any writeable memory system is presented. The test is applicable to almost any large memory system, and may be implemented entirely under software control, or with hardware support for maximum speed. This test is completely independent of any hardware monitoring, such as parity checking, that may be used while the memory system is in actual operation. (Image Omitted)

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Method for Address Fault Detection

A method of providing a quick and rigorous diagnostic test for addressing faults and individual stuck data bits in any writeable memory system is presented. The test is applicable to almost any large memory system, and may be implemented entirely under software control, or with hardware support for maximum speed. This test is completely independent of any hardware monitoring, such as parity checking, that may be used while the memory system is in actual operation.

(Image Omitted)

A method is presented here which utilizes only the normal address and data circuitry necessary for basic system operation, providing a test that does not require any dedicated checking circuitry, and which, by its nature, provides a basic test of each individual memory cell and also provides a nearly absolute and total check of each individual addressing circuit element. The test involves storing special test patterns into the actual memory cells in a test mode which is mutually exclusive with normal system functioning.

The following is the recommended test procedure for locating storage addressing faults and any individual bit fails in a minimum amount of time: 1. Select any pattern (e.g., 0000...) and its complement (1111...) matching the width of one word of storage. The patterns may be selected to detect any pattern sensitive faults between bits of the word if desired. 2. Store to every address in the memory system one address at a time, selecting one or the other of the above patterns depending on the parity of the address being stored to, starting at the lowest and ending at the highest address.
3. Fetch the data stored by the previous step, comparing all data to the known stored pattern. Any data that does not match can be caused by bad storage cells or addressing faults. The test does not distinguish between the two, but normally either fault is unacceptable, so it doesn't matter since the failing part must be replaced in either case. In most cases, unless a known good memory as large as the memory under test is available to remember the stored patterns, the same algorithm used to select the data for the store must be used again to generate the expected data during the fetch.
4.Store again to every address in the memory system, this time using the opposite patterns of those stored previously. These stores must be done beginning at the highest and ending at the lowest address. 5. Fetch the data stored in the previous step, again comparing against the known stored pattern to test for incorrect data (the order of the fetches is not important).

ECC correction, if used, must be disabled during this test.

The addressing circuitry will be assumed to fail in one of three modes: 1.A store and/or fetch fails to access any storage location. 2.A store and/or fetch accesses the wrong location instead of the location that was intended. 3.A store

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and/or fetch accesses the wrong location in addition to the location...