Browse Prior Art Database

Address Chaining Scheme to Provide Simultaneous-Multiple-Write Capability for Memory

IP.com Disclosure Number: IPCOM000035185D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Chang, PC: AUTHOR [+3]

Abstract

This disclosure describes a method to implement random access memory (RAM) with the capability of writing the same contents to multiple consecutive locations simultaneously. This feature substantially increases the memory updating speed, and thus reduces the potential bottleneck of the speed in applications such as controlling time-division- multiplex (TDM) switches.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Address Chaining Scheme to Provide Simultaneous-Multiple-Write Capability for Memory

This disclosure describes a method to implement random access memory (RAM) with the capability of writing the same contents to multiple consecutive locations simultaneously. This feature substantially increases the memory updating speed, and thus reduces the potential bottleneck of the speed in applications such as controlling time-division- multiplex (TDM) switches.

The conventional RAM is basically constructed using a single access scheme. Given an address location, a data unit in lengths of a bit, a byte, a half word or longer units can be fetched or stored. Normally, to access memory cells at one location takes a memory cycle. Therefore, it will take multiple memory cycles to access multiple locations.

We observed that in some application of RAM, it is desirable to store the same contents into multiple locations simultaneously. These multiple locations are usually consecutive. One example occurs in the design of TDM switch such as the Bitswitch. It uses RAM to store the

(Image Omitted)

switch connection table in which the contents are read out to control the switch connection operations in each time slot. A new connection is set up by writing the new connection information into the corresponding memory location. In a TDM digital switching system, one time slot allows a channel to transmit information bits at a fixed rate (e.g., 64 Kbps). When a higher bandwidth is needed by a channel such as H-channel (6 x 64 Kbps) or T1-channel (24 x 64 Kbps), the same contents are written into 6 (H-channel) or 24 (T1-channel) locations of the memory. As a result, multiple updates in conventional RAM generates serious delay and makes the switch controller a bottleneck. We herein introduce an approach using the address chaining scheme to fix the problem so that writing the same contents to multiple locations can be done in one memory cycle.

In a two-dimensional memory organization, it uses a row and a column address decoders to interpret the address and to locate the memory cell. Each decoder can only enable one of its output lines at a time. Thus only one location, the intersection of two enable lines, can be accessed. The address chaining scheme, as shown in Fig. 1, modifies the row address decoding mechanism to enable multiple output lines and thus to access multiple memory locations.

It uses two row address buses to indicate the start and the stop locations of the memory cells to be accessed. For simplicity the multiple locations accessed are constrained to have the same column address. Therefore, the column address decoder does not need modification.

Outputs of both row decoders are then fed into a Fill-In Logic which enables all locations between the start and the stop row addresses. The Fill-In Logic consisting of n elements, where n=2**k, k is the number of bits in the row address buses, performs the function Qi = Si + bar(Ri-1) Qi-1 <= i <= n-1, Q-

1

...