Browse Prior Art Database

Delay Line Multiplexing for a 4.5/3 Megabyte Programmable Channel

IP.com Disclosure Number: IPCOM000035218D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 95K

Publishing Venue

IBM

Related People

James, PN: AUTHOR

Abstract

The logic described below shows how the asynchronous interface clocks are generated for both the 4.5 megabyte channel and the 3 megabyte channel from one set of delay lines for each data-handling mechanism. (Image Omitted)

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Delay Line Multiplexing for a 4.5/3 Megabyte Programmable Channel

The logic described below shows how the asynchronous interface clocks are generated for both the 4.5 megabyte channel and the 3 megabyte channel from one set of delay lines for each data-handling mechanism.

(Image Omitted)

The Delay lines are the conventional channel implementation method for creating interface clocks to deskew data and set out bound tag lines on an OEMI channel. The deskew specs are different for a specific data rate and so the requirements for a 4.5 megabyte channel are completely different than for 3 megabyte channel. The following logic demonstrates the uses of a single set of delay lines to handle both data rates. Fig. 1 shows the basic layout of the interface between the Parallel Interface Adapater (PIA) chip and the Parallel Channel Driver Receiver (PCDR) chip. Notice that there is both a 0 and a 1 data- handling mechanism with an associated internal delay line. This internal delay is created by a series of latches and is substantially less critical (in tolerance) than the other signals. Fig. 2 shows the actual clock generating logic. The specific clocks generated are a function of a software programmable bit in the PIAs mode register. Fig. 3 shows the timing relationships at the various data rates.

(Image Omitted)

Notice that the I2_clk of the 4.5 megabyte mode becomes the I1_clk of the 3 megabyte mode. The timing of these pulses in conjunction with the tolerances of both P...