Browse Prior Art Database

Page Transfer Hardware Assist for Digital Signal Processor

IP.com Disclosure Number: IPCOM000035225D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR [+2]

Abstract

Most of current generation digital signal processor (DSP) devices have a limited data addressability. For example the 10 MHz IBM DSP can address 4 K half-word (12 bits). For addressability extension, a paging register is used, which contains the most significant bits (MSBs) of the address, which is loaded via a store operation by the signal processor. This generates overhead cycles in the case of data transfer from one page to another. Fortunately, in most of signal processing functions, transfers between pages are implemented on a buffer basis. So, one can suppress the overhead due to the paging register loading and reloading operations, through a simple mechanism based on a control register CNTREG connected to an I/O of the DSP.

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Page Transfer Hardware Assist for Digital Signal Processor

Most of current generation digital signal processor (DSP) devices have a limited data addressability. For example the 10 MHz IBM DSP can address 4 K half-word (12 bits). For addressability extension, a paging register is used, which contains the most significant bits (MSBs) of the address, which is loaded via a store operation by the signal processor. This generates overhead cycles in the case of data transfer from one page to another. Fortunately, in most of signal processing functions, transfers between pages are implemented on a buffer basis. So, one can suppress the overhead due to the paging register loading and reloading operations, through a simple mechanism based on a control register CNTREG connected to an I/O of the DSP.

Before starting the transfers, the control register is set with a proper value indicating the originating and final pages in the considered move operation. This value is then used to set up the proper page MSB of the RAM in the paging register PAGREG by decoding in the control logic the pre-fetched instruction (recognizing a read or write operation).

For example, the 16-bit control register contains in the lower byte the 8 MSBs of the final RAM page, and in the higher byte, the 8 MSBs of the originating RAM page, allowing transfers between 256 4K RAM pages without overhead cycles.

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