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Error Correction Codes WITH ADDRESS CHECKING

IP.com Disclosure Number: IPCOM000035242D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Mann, TL: AUTHOR

Abstract

As memory chip density and system memory capacity increase so does the susceptibility for failures. To increase the reliability of the memory chips, error correcting codes (ECCs) are frequently utilized.

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Error Correction Codes WITH ADDRESS CHECKING

As memory chip density and system memory capacity increase so does the susceptibility for failures. To increase the reliability of the memory chips, error correcting codes (ECCs) are frequently utilized.

While memory is organized to store data in increments of 2n bits, in most cases the ECC check bits required to check the data have the capacity to check more than 2n bits. Consequently, the full checking capability of the code is not used. To utilize the full potential of the code, limited address checking could be incorporated into the design. This would help insure that the data retrieved is not only correct but also that it comes from the correct location.

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CONVENTIONAL ECC IMPLEMENTATION

The conventional structure for implementing ECC is shown in Fig. 1. Since the data is stored unaltered this is for a linear systematic block code.

When data is written to memory, check bits are generated and stored with it. When the data is read from memory the check bits are regenerated and compared with the stored check bits to determine a syndrome. If an error is present, the syndrome is used to determine if it is correctable. If it is correctable, the syndrome is also used to locate the bit in error and correct it.

An example of a class of ECC are the Hamming codes. A Hamming code can correct all single bit errors and detect all double bit errors. Using three check bits, a (7,4) Hamming code, up to four data bits would be covered. With four check bits, a (15,11) Hamming code, up to 11 data bits would be covered. Consequently, for an eight-bit data byte, four check bits would be required by the code. ECC WITH ADDRESS CHECKING

While the conventional ECC structure will detect data errors, it provides no assurance on whether the data came from the correct address. For example, if two address decoder lines were shorted the data in memory would be overlayed. When retrieved, the overlayed data would be incorrect even though the syndrome would not indicate an error. To incorporate address checking, the conventional ECC structure could be modified, as shown in Fig. 2. The change is to add a parity generator for the address. The number of parity bits generated would be the maximum number of data bits covered by the code less the actual number of data bits used in the design.

When writing to memory, the parity bits would be concatenated with the data bits for the check bit generation. However, only the dat...