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Avoiding Address Generation Delays Using the Delay Overlap Prefetch Table

IP.com Disclosure Number: IPCOM000035247D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+4]

Abstract

A history-based, table-driven approach to overlapping certain I (Instruction) Unit delays in high performance computers with target instruction access delay for the next taken branch has been shown in [*]. This Delay Overlap Prefetch Table (DPT) is accessed when an address generation interlock, among other conditions, is detected in the I Unit; it delivers the target address of the next taken branch based on previous execution. Thus, the interlock delay is overlapped with the branch target access delay, and there is no delay when the taken branch is subsequently decoded.

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Avoiding Address Generation Delays Using the Delay Overlap Prefetch Table

A history-based, table-driven approach to overlapping certain I (Instruction) Unit delays in high performance computers with target instruction access delay for the next taken branch has been shown in [*]. This Delay Overlap Prefetch Table (DPT) is accessed when an address generation interlock, among other conditions, is detected in the I Unit; it delivers the target address of the next taken branch based on previous execution. Thus, the interlock delay is overlapped with the branch target access delay, and there is no delay when the taken branch is subsequently decoded.

The present technique shows how this DPT provides additional opportunity to eliminate address generation interlock delays on branch instructions.

The distance between the interlock and the next taken branch (of a similar measure, in halfword lengths) is used to identify the taken branch in the table for increasing the prediction accuracy. The DPT delivers these identification bits (IDBITS) along with the predicted target address of the next taken branch instruction (PTA) when the table is accessed during an interlock. A method of avoiding AGI (Address Generation Interlock) on branch instructions using this information is outlined below.

When a branch instruction is decoded, the IDBITS are used to determine if the target address provided by the table belongs to the branch being decoded.

If it does not, then the prediction indicates that the branch was previously executed in the memory span of the table and was not taken on the previous execution. In this case the AGI on the branch being decoded can be overridden because the target instructions are most lik...