Browse Prior Art Database

Storage Subsystem Request Finite State Machine

IP.com Disclosure Number: IPCOM000035252D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Gibson, KP: AUTHOR [+5]

Abstract

This technique allows a storage subsystem's hardware to control multiple types of storage devices (hard disk, tape, diskette) concurrently from the same hardware card. It also improves performance of storage subsystem IOP microcode when performing data transfer operations to hard disk, tape and diskette devices by using a Request Finite State Machine to control the transfer of data between from the host system and the devices.

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Storage Subsystem Request Finite State Machine

This technique allows a storage subsystem's hardware to control multiple types of storage devices (hard disk, tape, diskette) concurrently from the same hardware card. It also improves performance of storage subsystem IOP microcode when performing data transfer operations to hard disk, tape and diskette devices by using a Request Finite State Machine to control the transfer of data between from the host system and the devices.

A certain microprocessor-based I/O processor attaches storage devices to an I/O bus via an implementation of the ANSI IPI-3. It performs the physical conversion between the I/O bus and the IPI-3 bus as well as command and status conversion between the Storage I/O, Common I/O, and IPI-3 architectures. This I/O processor is an I/O Bus Unit, and it serves as a hard disk/tape/diskette storage subsystem controller.

The I/O processor is packaged on a 4-wide 6-high card inside the host system along with the CPU, memory, etc. Fig. 1 shows the organization of its internal hardware. The hardware consists of:

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The Control Processor, a Motorola M68000 microprocessor. * The Direct Memory Access Controller (DMAC) which controls memory accesses on the DMA bus. * The System Adapter (DA) which interfaces the processor to the SPD bus. * The Device Adapter (DA) which interfaces the processor to the DFCI bus. * The 512-Assist Counter which generates interrupts at host page boundaries. * The Bus Isolator which arbitrates accesses between the 68K bus and the DMS bus. * The Byte Alignment Unit (BAU) which aligns data and checks parity in DMA memory. * The Interval Timer which can be programmed to generate periodic interrupts. * The DMA Memory where data is buffered between the host system and the storage devices. * The Control Store where microcode is stored. * The ROS where power-on reset and IPL code is stored.

Microcode for the storage subsystem is divided into components based on the functions provided. Hardware Control (HWC) microcode services hardware interrupts and provides a logical interface between the hardware and the other microcode components. These components include Bus Transport Mechanism (BTM) which processes requests to open and close connections to resources, Device Manager (DEV) which processes SIOA requests to read and write to storage devices, and Maintenance Contr...