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Control Mechanism for a Packet Bus Communication Controller

IP.com Disclosure Number: IPCOM000035262D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 47K

Publishing Venue

IBM

Related People

Ofek, Y: AUTHOR

Abstract

This article describes a hardware mechanism for controlling a communication controller operation. The switching part of the controller is a packet bus, which is also used for implementing a random access function between the node controller and each of the switch ports. Using this mechanism it is possible to transfer state and control information (message passing in hardware) between the switch ports and between adjacent nodes. The control mechanism exploits the broadcast properties of packet bus and, by this, demonstrating an additional advantage of having a shared medium switch. The control operation over the packet bus is independent of the packet switch function.

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Control Mechanism for a Packet Bus Communication Controller

This article describes a hardware mechanism for controlling a communication controller operation. The switching part of the controller is a packet bus, which is also used for implementing a random access function between the node controller and each of the switch ports. Using this mechanism it is possible to transfer state and control information (message passing in hardware) between the switch ports and between adjacent nodes. The control mechanism exploits the broadcast properties of packet bus and, by this, demonstrating an additional advantage of having a shared medium switch. The control operation over the packet bus is independent of the packet switch function.

The basic concept which guides this design is that the nodes or, more specifically, the link adapters (the switch ports) do not operate in an empty space; they are connected to other link adapters on the adjacent nodes. Thus, the scope of the node control should includes its immediate neighbors. This approach is very important for implementing distributed data link control algorithms, and for fault tolerant.

The control mechanism has three parts: 1. Random access - by means of this mechanism the node controller (NC) can access and modify directly, via the packet bus a control memory space on each of the link adapters (LAs). From the controller point of view this memory space is part of its physical

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memory. Using the random access mechanism the node controller can broadcast state information to all the link adapters, and can control the multiple data paths through the switch. 2. Interrupt - the link adapters will use this mechanism for requesting asynchronously service from the node controller. The controller then will access the adapter's control space, for determining the nature of the request. 3. Hardware message passing between two adjacent nodes - by means of this mechanism a link adapter on one node can transfer state information to the control space of a link adapter on an adjacent node.

The objectives of these mechanisms are to enable the flow of control and state information between the following subsystems: 1. NC to LA - node controller program its link adapters. 2. LA to NC - link adapter requests the service of its node controller. 3. LA to LA - communication between link adapters on two adjacent nodes. 4. NC to NC - communication between node controllers on two adjacent nodes.

The control mechanisms are not aimed to any specific data link control protocol. The goal is to provide effective means for controlling high speed networks by using the packet bus. In such networks the time constraints will not enable the implementation of distributed control and fault tolerant by using only software message passing. Furthermore, these control mechanisms will enable increasing the "self-awareness" of the node, such that the node will be able to detect, diagnose and recover from failure in a v...