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Reduced Pattern Set and Related Test Algorithm for Data Path Test

IP.com Disclosure Number: IPCOM000035264D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Erpeldinger, B: AUTHOR

Abstract

This article describes an efficient algorithm to be used in data path tests like registers, data bus, arrays, etc. It may be useful for people involved in machine architecture, hardware design, test, and diagnostic design.

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Reduced Pattern Set and Related Test Algorithm for Data Path Test

This article describes an efficient algorithm to be used in data path tests like registers, data bus, arrays, etc. It may be useful for people involved in machine architecture, hardware design, test, and diagnostic design.

When testing an n-bit data path, the following tests have to be done: 1. Check that no bit is stuck to zero. 2. Check that no bit is stuck to one. 3. Check that no short-circuit or "crosstalk" exists between any couple of bits. (The physical implementation may cause bits not logically adjacent to be physically adjacent; therefore, the best solution is to test all couples of bits, even if not logically adjacent.) 4. Minimize the number of test patterns used to reduce test time. 5. Clear the path at the end of the test. Tests 1 and 2 are easy to achieve.

One good method for performing test 3 is known as "the walking one patterns": each bit is set to one while the others are maintained at zero. In this case the number of test patterns is equal to the number of bits in the data path, plus one for reset.

According to this article, the number of test patterns may be reduced as follows: Considering the ordered patterns of the successive values set for each bit, the same patterns for any couple of 2 bits must never be used. The simplest way may be to respectively set each bit with values giving patterns 1 to n.

Example of test patterns for n bits between 1 and 32 1 32 1 0 1 0 1 0 1 0 1 0...