Browse Prior Art Database

Efficient Memory Allocation for Packet Data Transfers

IP.com Disclosure Number: IPCOM000035269D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

A technique is described whereby an efficient method of random-access memory (RAM) buffer size and allocation enables long message packet data transfers to be processed without occurrence of overflows or underflows in the buffers. An integrated circuit with input/output buffers and controls is described.

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Efficient Memory Allocation for Packet Data Transfers

A technique is described whereby an efficient method of random-access memory (RAM) buffer size and allocation enables long message packet data transfers to be processed without occurrence of overflows or underflows in the buffers. An integrated circuit with input/output buffers and controls is described.

When packet data is transmitted, or received, long messages require the efficient transfer of data so that overflows or underflows will not occur at the memory buffering units. In addition, control words associated with each data packet and message packets, without data, must be properly handled. The concept described herein utilizes an integrated circuit to provide efficient sequencing and buffering of incoming and outgoing packets and to transfer the data to and from a large main memory. The integrated circuitry is designed so that it will function with both low- and high-speed adapter cards offering three distinct options: 1) The data bus width between the packet RAM buffer and main storage may be either sixteen or thirty-two bits wide. 2) A dual-port memory may be used. 3) The data rate between the packet RAM buffer and main storage is programmable, thereby providing data transfers every 100, 200, 300, or 400 ns.

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The block diagram, as shown in Fig. 1, incorporates the integrated circuit in the control of channel bit transfers between main memory and microprocessor. In the use of the concept, the following implementation criteria is considered: o That the maximum packet size is thirty-two transfers of thirty-two bits each, plus control words. o That the integrated circuit chip will automatically transfer data between the RAM buffer and the channel. o That the microprocessor will provide a pointer to the main storage location where data transfers to or from the RAM buffer will take place. o That the microprocessor will analyze input control words and generate the required output words. o That the packet hardware will control the transfer of packet data from main memory to the RAM buffer and then transmit the data to another adapter when the channel is available. o That the data path between the main memory and the RAM buffer may be either sixteen or thirty-two bits wide.

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o That messages may be relatively long and consist of a large number of packets. o That the channel transfer rate is one 32-bit word every 100 ns.

As an example of the use of the integrated circuitry, a "Data Concentrator" (DC) can be implemented where twenty or more adapters can send data to the packet hardware. In the implementation of the DC, data is properly formatted and retransmitted within the integrated circuit. In the determination of the RAM size and configuration, the device determines the following parameters: a) The number of successive packets that can be sent over the channel to a given adapter without a buffer overflow. b) The amount of time required for the mic...