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Low Temperature Shallow Trench Device Isolation of Semiconductor Material

IP.com Disclosure Number: IPCOM000035277D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Bronner, G: AUTHOR [+2]

Abstract

A technique is described whereby ion implanted polysilicon is used as an insulator to provide low-temperature shallow-trench isolation of silicon devices used in the manufacture of integrated circuits. Ion implantation is used, instead of a long thermal process, to create extremely small isolation regions to provide insulation. By eliminating the high temperature process requirement to provide isolation, smaller device spacing is attainable, thereby minimizing the ultimate size of integrated circuits.

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Low Temperature Shallow Trench Device Isolation of Semiconductor Material

A technique is described whereby ion implanted polysilicon is used as an insulator to provide low-temperature shallow-trench isolation of silicon devices used in the manufacture of integrated circuits. Ion implantation is used, instead of a long thermal process, to create extremely small isolation regions to provide insulation. By eliminating the high temperature process requirement to provide isolation, smaller device spacing is attainable, thereby minimizing the ultimate size of integrated circuits.

Silicon devices typically utilize local oxidation of the silicon to provide the required isolation of the devices which make up the circuit. The minimum isolation between devices is set by two factors: (1) the sloping of the sidewalls of the isolation region and (2) the lateral diffusion of the dopant below the isolation. Prior art considered reducing the slope of the sidewall by digging a trench with reactive ion etching, protecting the vertical sidewalls with silicon nitride and then oxidizing either the single crystal silicon or depositing polysilicon into the trench and thermally oxidizing it. Although these techniques eliminate the sloping of the sidewalls of the isolation regions, they do not address the problem of lateral diffusion of the dopant below the isolation region. The concept described herein continues to use reactive ion etching to form an isolation with the vertical sidewall; however, instead of using high temperature oxidation of silicon to form an insulating layer, ion implantation is used to convert a polysilicon layer into an insulation layer. By eliminating the high temperature step, lateral diffusion of the dopant below the isolation layer is minimized, allowing much smaller device-to- device spacing.

Although the process described below is for n-well CMOS devices, the technique is applicable to all such technologies: 1) A thin layer of silicon dioxide (SiO2) is grown on the silicon substrate. A thick layer of Si3N4 is deposited using chemical vapor deposition (CVD). These layers are patterned photolithographically and etched using reactive ion etching (RIE). 2) An RIE process is...