Browse Prior Art Database

Level-Sensitive Scan Design Digital Portion of Phase-Locked Loop and Data Separator

IP.com Disclosure Number: IPCOM000035278D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Kocis, T: AUTHOR [+2]

Abstract

This article describes the use of level-sensitive scan design (LSSD) methodology to implement the digital portion of an analog phase-locked loop (PLL) and data separator. This LSSD is equivalent to a design utilizing edge-sensitive latches but has the advantages provided by LSSD high testability and no race conditions.

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Level-Sensitive Scan Design Digital Portion of Phase-Locked Loop and Data Separator

This article describes the use of level-sensitive scan design (LSSD) methodology to implement the digital portion of an analog phase-locked loop (PLL) and data separator. This LSSD is equivalent to a design utilizing edge- sensitive latches but has the advantages provided by LSSD high testability and no race conditions.

Fig. 1 is a block diagram illustrating an entire PLL and data separator. It is essential to proper operation of the PLL and data separator that the divider output and MUX control be synchronous to the voltage control oscillator (VCO) output.

Fig. 2 is a block diagram of the LSSD disclosed herein. The VCO output is used to generate LSSD B and C clock. These clocks are synchronous to the VCO output. These signals are used to clock level- sensitive latches in the divider and MUX control. Therefore, the design requirement that the divider output and MUX control must be synchronous to the VCO output is met.

The clock generation circuitry operates either in test mode or functional mode. The functional mode is selected by holding the -Test/+Funct input high. The test mode is selected by holding the -Test/+Funct input low. In functional mode, it operates as described

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above. In test mode, the C CLK Test input can be gated through to the C clock output of the clock generation by holding the VCO output low. The B CLK Test input can be gated through to the B cl...