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TTL Clock Receiver

IP.com Disclosure Number: IPCOM000035284D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR

Abstract

Receiver circuits are shown for setting special levels, such that independent control is afforded for setting 0/1 levels and determining noise margins while another set of devices is utilized to determine performance parameters.

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TTL Clock Receiver

Receiver circuits are shown for setting special levels, such that independent control is afforded for setting 0/1 levels and determining noise margins while another set of devices is utilized to determine performance parameters.

In some multi-chip systems, each chip contains an independent clock. Synchronization is provided by a common system clock. Clock generation delays cause skew between chips and degrade system performance. In some cases, a master clock interface signal may be generated in a different technology (TTL versus CMOS), such that the respective logic is accommodated. In some cases the frequency of the system clock is a multiple of the chip frequency. Receivers are shown for translating special levels and receive a master clock to be divided by two.

The low-level receiver shown in Fig. 1, consists of separate controls for N and P devices in an inverter. Two double inverter sets (T1/T2, T1A/T2A and T3/T4, T3A/T4A) are used to control the output inverters ((T5/T6 and T7/T8). High- and low-level signal detection is accomplished with different devices in the control inverter sets. This technique affords a means for controlling the inputs for devices T5 and T6 separately. The inputs signal may be TTL or GPI levels and the output is full CMOS levels. The control devices may alternately be adjusted so that the output of the receiver is symmetrical, with equal rise and fall times, and equal turn-on and turn-off delay.

Referring to Fig. 2...