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Logical Method for Sequential Bit Counting for Use in Single or Multiport Memories

IP.com Disclosure Number: IPCOM000035290D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Hovis, WP: AUTHOR [+3]

Abstract

A method of sequential selection of memory bits is achieved by providing the necessary logic within the data stream. Data is received by registers in a sequential manner because additional logic instructions would be needed to perform unscrambling of the data. This circuit allows the data to be read or written in minimum time.

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Logical Method for Sequential Bit Counting for Use in Single or Multiport Memories

A method of sequential selection of memory bits is achieved by providing the necessary logic within the data stream. Data is received by registers in a sequential manner because additional logic instructions would be needed to perform unscrambling of the data. This circuit allows the data to be read or written in minimum time.

To achieve high density memory designs, such techniques as folded bit lines and sharing common diffusions are used. This leads to scrambling of a logical count for sequentially accessing bits.

Shown in the figure is a decoder circuit having four outputs Vb(1-4), which are used to access bits in a memory array. During standby, nodes NOR(1-4) are precharged to high supply voltage VDD through devices T5x. During standby time, output signal lines Vbx, input signal line VBP and address lines T(0-2) are all grounded. A decoder is selected by driving signal line VBP to Vdd. The appropriate field of addresses is applied and the output signal Vbx is driven to VDD by signal Vbb, through device T1x. Norx nodes are restored to VDD and ground, respectively, in the standby time through signals VDR, VBL and VWR.

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By performing an Exclusive NOR decode on those addresses that require unscrambling, a sequential bit count can be performed. The logic table above describes the corresponding Vb decode as a function of a three address (A0, A1, A2) field.

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