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IEEE Arithmetic Using a HEX Floating Point Arithmetic Unit

IP.com Disclosure Number: IPCOM000035299D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 35K

Publishing Venue

IBM

Related People

Cocke, J: AUTHOR [+3]

Abstract

A method is described to imbed a IEEE floating point word in a HEX floating point word and to show how the hex floating point operations must be modified to perform IEEE style operations. The principal modification is to the treatment of the guard digit and to the extra considerations for rounding and unusual operands.

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IEEE Arithmetic Using a HEX Floating Point Arithmetic Unit

A method is described to imbed a IEEE floating point word in a HEX floating point word and to show how the hex floating point operations must be modified to perform IEEE style operations. The principal modification is to the treatment of the guard digit and to the extra considerations for rounding and unusual operands.

This method describes how a design for a floating point unit which operates in hexadecimal radix can be extended to also perform floating point arithmetic according to the IEEE standard.

The description is specific for IEEE and HEX 64-bit formats. These motions can be applied to 32-bit formats or to any similar binary and hexadecimal formats. A HEX 64-bit format specifies: a) a 1-bit sign b) a 7-bit exponent for the power 16, in excess 64 notation. c) a 56-bit fraction in which each 4 bit nibble is regarded as a hexadecimal digit. In a normalized hex fraction, the heading nibble must be non-zero. An IEEE 64-bit format specifies: a) a 1-bit sign b) an 11-bit exponent for the power 2, in excess 1023 notation c) a fraction of 52 bits. For normalized numbers, there is an implicit "one" bit to the left of the fraction. The method involves the following topics: a) An internal floating point representation convenient for a hexadecimal arithmetic unit. b) Conversion from standard IEEE and HEX formats into the internal format. c) Conversion from internal format to standard IEEE and HEX formats. d) Arithmetic on internal format floating point numbers. A) The internal representation of a floating point number consists of 3 components: 1. a 1-bit sign, called S 2. a 56-bit unsigned fraction, called F 3. a 10-bit exponent, called E, which must represent unbiased exponents in the range -512 & E < 512 The representation of E may be twos complement, binary sign-magnitude, or excess -256. The choice is irrelevant. The description, however, is in terms of an unbiased repre sentation. B) 1) To convert a hex format floating point number consisting of sign s, fraction f, and exponent e (in excess 64 notation) to internal format: S=s F=f E=e-64 2) To convert an IEEE format floating point number con sisting of sign s, fraction f, and exponent e (in excess 1023 notation) to internal format, 3 cases are considered
a) Infinities and NaNs, i.e., e=2047 S=s E=511 F=f `0000' b) Denormalized numbers and zeros, i.e., e=o S=s E=-255 F=f `00' c) Normal numbers, i.e. 1 & e & 2046 S=s E = [ (e-1019)/4] ([-] is the floor operator) F = 1 f R zeros, where R = e-1019 (mod 4).

In cases b) and c) sufficient leading zeros are provided to make a 56-bit fraction. C) To convert internal format numbers to external format: We first introduce some notation. Bits in a field will be numbered from left to right, with the most significant bit having number 0. Thus we write F0-3 to represent the leading 4-bit nibble of the internal representation fraction. 1) To convert an internal number of conventional HEX f...