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Arrangement for Simulating Flutter During the Reading of Magnetic Stripes on Cheque Cards, Etc

IP.com Disclosure Number: IPCOM000035309D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Maier, H: AUTHOR

Abstract

As cheque cards with magnetic stripes are read, flutter (variations of synchronism) may occur, leading to increased error rates. Such flutter is simulated by the proposed arrangement in order to detect and correct read data affected thereby. For this purpose, a data flow, such as that emanating from the read head of a read unit, is produced and subjected to flutter.

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Arrangement for Simulating Flutter During the Reading of Magnetic Stripes on Cheque Cards, Etc

As cheque cards with magnetic stripes are read, flutter (variations of synchronism) may occur, leading to increased error rates. Such flutter is simulated by the proposed arrangement in order to detect and correct read data affected thereby. For this purpose, a data flow, such as that emanating from the read head of a read unit, is produced and subjected to flutter.

The proposed arrangement produces the flutter electronically, if necessary, under computer control. Thus, measures taken to increase the reading realiability may be rapidly and reproducibly tested, as the kind and the rate of the flutter are arbitrarily selectable.

The arrangement consists of a PC 1 or a similar device which supplies a data flow 2 corresponding to that encountered during the reading of the magnetic stripe. The flutter is generated on an analog delay line of a bucket brigade circuit 3 comprising some 1000 to 2000 capacitors 4. Capacitors 4 are interconnected by CMOS switches 5 integrated on the same chip. Amplifiers are provided at regular distances. Circuit 3 is controlled by two phase-opposed clock signals D1 and D2 which close every other CMOS switch 5 of the brigade, so that an analog or digital signal 2, applied to the input, is fed from one capacitor to another until it finally reaches the output as signal 2'. The delay occurring is directly proportional to the number of integrated capa...