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Instruction Cache Miss State Machine and Cache Miss Request

IP.com Disclosure Number: IPCOM000035314D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Boufarah, EJ: AUTHOR [+3]

Abstract

A common approach to providing instructions for pipelined processors to minimize the instruction wait time is to prefetch instructions. When a cache miss occurs on an address that corresponds to a prefetched instruction, the processor may or may not actually need that instruction, since this depends upon the nature of instructions currently executing or waiting for execution by the pipeline. If it turns out that the processor did indeed require those instructions, then the immediate handling of that cache miss will minimize the pipeline wait time. If one of the instructions in the pipeline is a branch-type instruction, then the traffic resulting on memory busses from the prefetch may be undesirable.

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Instruction Cache Miss State Machine and Cache Miss Request

A common approach to providing instructions for pipelined processors to minimize the instruction wait time is to prefetch instructions. When a cache miss occurs on an address that corresponds to a prefetched instruction, the processor may or may not actually need that instruction, since this depends upon the nature of instructions currently executing or waiting for execution by the pipeline. If it turns out that the processor did indeed require those instructions, then the immediate handling of that cache miss will minimize the pipeline wait time. If one of the instructions in the pipeline is a branch-type instruction, then the traffic resulting on memory busses from the prefetch may be undesirable.

A technique to determine when to handle a cache miss based upon both concerns mentioned above is the following. Branch-type instructions waiting in the pipeline will prevent the immediate handling of a cache miss for a prefetched instruction, but instructions in the pipeline which may cause an interrupt do not delay cache misses for prefetched instructions. Note that this technique only applies to cache misses corresponding to prefetching, since addresses that are known to be needed are handled immediately in all cases.

This technique can be implemented in the following way. As each instruction is written into the instruction cache, a set of pre-decode tags are generated, one of which indicates that an instruction is a branch-type instruction. Once instructions are fetched from the cache arrays, they are pla...