Browse Prior Art Database

Software Reset to Second Processor Via Non-Maskable Interrupt

IP.com Disclosure Number: IPCOM000035322D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Peterson, GA: AUTHOR [+3]

Abstract

A method is provided for a master processor to reset a slave processor using a non-maskable interrupt, some hand-shaking bits in a register, and associated software.

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Software Reset to Second Processor Via Non-Maskable Interrupt

A method is provided for a master processor to reset a slave processor using a non-maskable interrupt, some hand-shaking bits in a register, and associated software.

Normal processor-to-processor communication by maskable interrupts or polling schemes require the slave processor to be in an expected state. The slave processor could be in an unexpected state as the result of a bus or processor error. If the slave processor is in an unexpected state, a software reset by normal communication methods is unreliable.

This method provides a mechanism by which a master processor can reliably reset a slave processor without a hardware reset.

Both hardware and software are required. The key pieces of this software reset mechanism are shown in Fig. 1.

When the master processor wishes to reset the slave processor, the following sequence occurs: 1. Master reset code issues a command which sets the 'Reset Request' and 'NMI from master' bits in the interrupt control register (See Fig. 2).
2. 'NMI from master' causes a non-maskable interrupt (NMI) to be issued to the slave processor. 3. The slave processor begins executing the slave reset code regardless of the state of the slave processor. 4. The slave reset code determines that the source of the NMI is from the master and that the 'Reset Request' bit is also active. 5. The slave reset code initiates a processor reset.

Step 3 is very important in that a software rese...