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Data ALIGNMENT Between I/O Buses

IP.com Disclosure Number: IPCOM000035340D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 132K

Publishing Venue

IBM

Related People

Barrett, WM: AUTHOR [+3]

Abstract

Some I/O buses require that data sent across them be aligned properly for the receiver. Other buses do not have this requirement, which means that the receiver must perform re-alignment to store data if the alignment does not match. Bus interface hardware must perform alignment of bytes to avoid violating this requirement without requiring wasteful copying of data by the processor. Whether the alignment is done in the sender or receiver is immaterial to this design. (Image Omitted)

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Data ALIGNMENT Between I/O Buses

Some I/O buses require that data sent across them be aligned properly for the receiver. Other buses do not have this requirement, which means that the receiver must perform re-alignment to store data if the alignment does not match. Bus interface hardware must perform alignment of bytes to avoid violating this requirement without requiring wasteful copying of data by the processor. Whether the alignment is done in the sender or receiver is immaterial to this design.

(Image Omitted)

The key to understanding the alignment problem is to look at storage as chunks of bytes instead of bytes. Storage is addressed as bytes, but the unit of transfer across the bus is chunks. If the starting address of a block of data is divisible by the length of a chunk in both processors, then there is no problem. In addition, if the data starts with the same offset from a chunk boundary in both processors, then there is no problem. However, if the data is not aligned the same way within a chunk in both processors, then there is an alignment problem. That is, if (address_in_unit_1 MODULUS chunk_length) µ= (address_in_unit_2 MODULUS chunk_length) then there is an alignment problem.

The simplest method of rectifying this is to have software allocate a new buffer and copy the data into or out of the buffer. When transmitting data that has to be realigned, the software would copy it to a buffer and set up the proper alignment; when receiving data, the software would receive it in a buffer and copy it to the final destination. The problems with this solution are that such copying: - takes processor cycles (even with a block transfer mechanism) - takes storage - ties up the storage subsystem - might be required frequently - might have to handle large amounts of data (as it would if there were unaligned transfers to or from a disk system)

Herein, "internal" means the bus and hardware inside the bus unit, and "external" means the I/O bus that the bus unit connects to. The alignment mechanism connects the internal and external buses.

The design adds an extra byte onto the bus interface hardware buffers on the internal data bus. The extra byte allows for saving of bytes and introduces them into the next internal bus cycle. The extra byte is only for alignment, and is not available outside of the alignment mechanism.

This mechanism is a general solution, requiring one "extra" byte for every byte of "shift" that is required (generally, one less than the number of bytes on the shorter of the two buses to be aligned). This section describes aligning a four-byte bus and a two-byte bus, and aligning two four-byte buses.

Aligning a two-byte bus and a four-byte bus requires a three-way selector on the inputs of byte (0) and (1) of the right-hand buffers, and no selector on byte (2) of those buffers. It requires a two-way selector on each byte of the left-hand buffers (refer to the illustrations in Fig. 1).

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The left-hand buffe...