Browse Prior Art Database

Miniature Thermal Switch

IP.com Disclosure Number: IPCOM000035344D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR [+4]

Abstract

By using very large-scale integration (VLSI) manufacturing processing techniques, an extremely small thermally actuated switch is constructed. Switches thus manufactured may be single throw (ST), normally closed current carriers that open with a current surge to provide circuit protection. Double throw (DT) switches may be constructed to re-route current flow at an upper current limit or upper chip temperature limit. Normally open switches may be constructed for chip temperature detection or used as current shunts actuated by chip temperature.

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Miniature Thermal Switch

By using very large-scale integration (VLSI) manufacturing processing techniques, an extremely small thermally actuated switch is constructed. Switches thus manufactured may be single throw (ST), normally closed current carriers that open with a current surge to provide circuit protection. Double throw (DT) switches may be constructed to re-route current flow at an upper current limit or upper chip temperature limit. Normally open switches may be constructed for chip temperature detection or used as current shunts actuated by chip temperature.

Referring to the figure which shows the structure of a DT switch, insulating layer 2 is first formed on silicon substrate 4. Insulating layer 6 is then deposited on layer 2, and a channel is etched in it. Polysilicon 8 is conformally deposited and is reactive ion etched (RIE) to partially fill the channel previously etched in insulator 6. A temporary construction material, e.g., parylene, is deposited and planarized to the level of the top surface of insulator 6. A two-layer conductive line 10 is next formed by deposition and etching. The bottom layer of line 10 is of conductive material with a coefficient of thermal expansion lower than that of an upper conductive material. The deposition of line 10 takes place at a temperature above normal chip operating temperature; therefore, there is a residual stress in line 10 at room temperature tending to bend line 10 upward. Because of adhesion to its substrate, line 10 remains flat.

An insulating layer 12 is then deposited having a thickness equal to line 10 and is etched to form an opening in layer 12 aligned with the parylene filled trench in layer 6....