Browse Prior Art Database

BICMOS LATCHUP PREVENTION SCHEME

IP.com Disclosure Number: IPCOM000035353D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Schmerbeck, TJ: AUTHOR [+3]

Abstract

This is a general circuit design scheme to prevent latch-up on chips containing both high current bipolar and CMOS circuits. The normal precautions of not pulling any chip pads above the most positive chip supply or below the most negative chip supply must still be followed. If the subcollector is not buried during the ACMOS process, the bipolar NPN transistors saturate early (at over a volt collector to emitter voltage at rated current). The absence of the subcollector also makes it easier to drive saturation currents into the chip substrate and thus have the potential for latchup. In general, any BI-CMOS process is subject to latchup if substrate currents get large enough.

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BICMOS LATCHUP PREVENTION SCHEME

This is a general circuit design scheme to prevent latch-up on chips containing both high current bipolar and CMOS circuits. The normal precautions of not pulling any chip pads above the most positive chip supply or below the most negative chip supply must still be followed. If the subcollector is not buried during the ACMOS process, the bipolar NPN transistors saturate early (at over a volt collector to emitter voltage at rated current). The absence of the subcollector also makes it easier to drive saturation currents into the chip substrate and thus have the potential for latchup. In general, any BI-CMOS process is subject to latchup if substrate currents get large enough. During very low power supply conditions, without taking any design prevention steps, virtually every bipolar transistor on the chip can be saturated, which can produce very large cumulative saturation currents. The BICMOS LATCHUP PREVENTION SCHEME - Continued scheme described herein prevents this mass saturation by shutting down the bipolar current source and voltage reference during these power-up and power-down conditions. A common voltage and current source reference was used for all circuits containing saturating bipolar devices to allow this global disable.

Since latchup is generally destructive to the chip when it occurs, it is also desirable to prevent its occurrence for momentary overcurrents or shorts during chip probing or testing. The key latch-up areas were again at output points where NPN emitter follower outputs could be shorted and produce large currents while saturating the NPN device itself. This would cause large substrate currents to flow. A special current limiting circuit is used which does not allow the output to saturate at large currents.

Fig. 1 shows a schematic of the circuit used to disable the chip reference during power-up and power-down conditions. The reference design has a single point where it may be disabled (G10), but multiple points and both polarities of disable in either voltage or current form are possible. The circuit incorporates a few tenths of a volt hysteresis so that noise on the power lines will not cause multiple switches of the output during power up or power down conditions. The circuit guarantees that the reference is disabled when the +5 volt supply is below 4 volts. R2 through R4 values are chosen such that when connector P5V (+5 volt supply terminal) is below 4 volts, Q2 is on and Q2 is off. Since T3 t...