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SELF-ALIGNED SUB-HALF MICRON GALLIUM ARSENIDE MESFETs AND SILICON MOSFETs

IP.com Disclosure Number: IPCOM000035364D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 85K

Publishing Venue

IBM

Related People

Brady, MJ: AUTHOR [+2]

Abstract

A technique is described whereby an improved fabrication process provides self-aligned sub-half micron GaAs MESFETs and Si MOSFETs by avoiding multi-level resists, lift-off techniques, as well as E-beam and X-ray lithographies. Described is a process that utilizes both optical and "chemical" lithography to fabricate sub-micron gate GaAs MESFETs and Si MOSFETs in one mask step.

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SELF-ALIGNED SUB-HALF MICRON GALLIUM ARSENIDE MESFETs AND SILICON MOSFETs

A technique is described whereby an improved fabrication process provides self-aligned sub-half micron GaAs MESFETs and Si MOSFETs by avoiding multi- level resists, lift-off techniques, as well as E-beam and X-ray lithographies. Described is a process that utilizes both optical and "chemical" lithography to fabricate sub-micron gate GaAs MESFETs and Si MOSFETs in one mask step.

In prior art, conventional optical photo-lithography and standard semiconductor processes were used to achieve sub-micron GaAs MESFET structures, utilizing a single level resist. Typically, the fabrication required numerous processing steps, such as incorporating lift- off, multi-layer resist structures and deep ultraviolet and electron beam lithography.

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The concept described herein simplifies the prior-art process by achieving small source-to-gate line widths and self-alignment through the use of optical lithography. The technique utilizes the property of a novlac base photo-resist system that allows the controlled diffusion of silicon into the resist. This process is termed "silylation", where the depth of the silicon diffusion is controllable and has a linear dependence with depth versus time.

For the fabrication of GaAs MESFETs, the process consists of a layer of resist spun coated onto a GaAs substrate that has been blanket coated with a refractory metal, such as tungsten, to a thickness of 100 nm. The resist is then exposed, developed and silylated in the vertical and horizontal directions to a depth of approximately 300 nm. After etching in an oxygen plasma, the remaining pattern is 300 nm wide by 600 nm high, as shown in Fig. 1.

The silylated pattern serves as a mask for patterning of the underlayer of tungsten by plasma etching or ion beam milling. Tungsten is a well known gate material which allows for aqueous anodization, forming a tungsten oxide. It has been well characterized in terms of its dielectric properties and breakdown strength. The reciprocal of the breakdown strength is approximately fifteen to twenty angstroms per volt. The tungsten oxide formed can then be controlled to a lateral dimension of approximately 100 nm with a v...