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Method of Reducing Emitter Coupled Logic Power Consumption by the Use of a Complementary Emitter-Follower Driver

IP.com Disclosure Number: IPCOM000035368D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Chuang, CTK: AUTHOR

Abstract

Disclosed is a method of reducing the power consumption of Emitter Coupled Logic (ECL) by using a complementary emitter-follower driver. This approach reduces the ECL power consumption by about 30-35% and enhances the driving capability of the ECL circuits. Fig. 1 and 2 illustrate alternative embodiments of an ECL NOR circuit including emitter-follower driver circuitry. The circuit of Fig. 1 basically resembles a conventional ECL NOR/OR gate except that additional emitter-follower transistors T4 and T5 are added and used to drive pull-down PNP transistors T6 and T7. In Fig. 1, pull-down PNP transistors (T6, T7) and pull-up NPN transistors (T8, T9) are configured as complementary emitter-follower drivers.

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Method of Reducing Emitter Coupled Logic Power Consumption by the Use of a Complementary Emitter-Follower Driver

Disclosed is a method of reducing the power consumption of Emitter Coupled Logic (ECL) by using a complementary emitter-follower driver. This approach reduces the ECL power consumption by about 30-35% and enhances the driving capability of the ECL circuits. Fig. 1 and 2 illustrate alternative embodiments of an ECL NOR circuit including emitter-follower driver circuitry. The circuit of Fig. 1 basically resembles a conventional ECL NOR/OR gate except that additional emitter-follower transistors T4 and T5 are added and used to drive pull-down PNP transistors T6 and T7. In Fig. 1, pull-down PNP transistors (T6, T7) and pull-up NPN transistors (T8, T9) are configured as complementary emitter-follower drivers.

When one or more of the inputs goes "HIGH", the switching current flows through load resistors R1 and R2, and node A assumes a "LOW" state (e.g., .3
V). Further, emitter-follower transistor T4 is turned "OFF" and node B assumes a "LOW" value of approximately VEE1 (e.g., -1.1 V). Because of the complementary emitter-follower configuration, VO is approximately equal to the intermediate value of the voltages at nodes A and B.

(Image Omitted)

The level of complementary output VO-- is determined by the voltages at nodes C and D. When one or more of the inputs goes "High", node C assumes a "HIGH" state (e.g., 1.1 V). Further, emitter-follower transistor T5 t...