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Integrated Input/Output Support Circuitry for Use With 80286/80386 Microprocessors

IP.com Disclosure Number: IPCOM000035371D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 9 page(s) / 153K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR

Abstract

A technique is described whereby integrated support input/output (I/O) circuitry and control programming is used in conjunction with 80286 and 80386 microprocessors to increase the performance and function of personal computer systems.

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Integrated Input/Output Support Circuitry for Use With 80286/80386 Microprocessors

A technique is described whereby integrated support input/output (I/O) circuitry and control programming is used in conjunction with 80286 and 80386 microprocessors to increase the performance and function of personal computer systems.

The integrated support chip is designed to be used in the I/O section of personal computer systems that utilize the Intel 80286 and 80386 microprocessors. It is designed to provide four key functions: 1) Programmable Interrupt Vectors - To allow any interrupt the ability to address any vector in the vector table of the processor. 2) Direct Memory Access (DMA) Dynamic Bus Sizing - To allow the DMA controller to transfer data to or from any size memory/ I/O device (8, 16 or 32 bit) without being pre-programmed for the device's size. Bus size signals are used during a cycle to access a device. 3) Software Compatibility - To allow the extension of DMA to 32-bits for Data/Address control and to provide maintenance and compatibility of DMA channels. 4) Adaptability - To enable a single I/O chip to function with both the 80286 and 80386 microprocessors.

The integrated I/O support circuit chip consists of four independent sixteen-bit counters 10, 11, 12 and 13, as shown in the figure. All four of the counters use the external input counter clock signal CLKIN and provide both binary or BCD counting.

Control word registers (CWRs) are selected by the Read/Write logic of the companion chip with an I/O address decode of 0043H and 0047H. If the processor does a write operation to the CWRs of the interval timer, the data is stored in the register and is interpreted as a control word used to define the operation of the counters. The CWRs can only be written into. Status information is available with the read-back command.

The counters are functionally identical. The only difference is in the control signals which control the gate inputs and the input clock signals. The output of each counter is connected differently. The following describes the control and output signals of each counter: - Counter 10 - Event timer - GATE is always enabled. - CLK is connected to the external CLKIN signal. - OUT is connected to the clock input of software resettable latch 14. The output of latch 14 is connected to the IRQ9 interrupt input of the companion chip's interrupt controller. The data input to latch 14 is tied to a logic 1 level. On a hardware reset or when the IRQ9 interrupt is masked or at the end of the second interrupt acknowledge cycle for the IRQ9 interrupt vector, the output of latch 14 is set high. - Counter 11 - Refresh Request - GATE is always enabled. - CLK is connected to the external CLKIN input. - OUT represents the Refresh Request (RR) signal where the rising edge of the OUT signal sets the Refresh Request through latch 15. The RR is prioritized with the DMA channel 5 request, through prioritizer 16, and drives the PREREQ output...