Browse Prior Art Database

Fast Roll Back Scheme of Cache Memory

IP.com Disclosure Number: IPCOM000035386D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+2]

Abstract

A technique is described whereby both fetch and store is completed in one cycle through the use of a roll back concept to reduce logic design complexity.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Fast Roll Back Scheme of Cache Memory

A technique is described whereby both fetch and store is completed in one cycle through the use of a roll back concept to reduce logic design complexity.

Typically, cache designs use a TLB comparison and/or cache directory look- up, which, in turn, tends to be the critical path in the cache accessing. The delay imposed in this path is much longer than other critical paths of the processor, such as address generation, and is normally sectionalized into two cycles. As a result, pipeline stages and design complexity is increased.

During a LOAD operation, a one-cycle access can be achieved by taking advantage of the locality of the program using MRU information [*]. For a STORE operation, however, the incorrect modification of the data for a miss is not acceptable. Therefore, a WRITE to the cache array cannot be performed until the TLB comparison and cache directory look-up are completed. Therefore, typical STORE operations cannot be completed in one cycle.

(Image Omitted)

The concept described herein utilizes roll back techniques, by using a row of specially designed memory cells (backup cells) in the memory array, to achieve both fetch and store operations in one cycle. During a STORE operation the data which may be modified is copied into the backup cells. Then the data is written into the array, using the MRU information, in one cycle.

In the case of a miss (the guess is wrong), the data which has been modified incorrectly can be recovered using the information saved in the backup cells. The input data can be written to the correct location according to the results of the TLB comparison and cache directory look-up in the next cycle.

The static random-access memory cache array is organized as 2K x 72 at the outputs, although other array sizes can be implemented. Physically, the 2K x 72 array is organized into four 36K array blocks, as shown in Fig. 1. The bitlines are separated from the 72 input/output (I/O) lines by means of bitline switches. The pass gate is controlled by the column decoder. A sense amplifier and an output register are used for each I/O line. The I/O line capacitance is quite large; therefore, a sense amplifier is used for each bitline so as to improve access time. The sense amplifiers are only activated during a read cycle.

(Image Omitted)

The circuit diagram of the backup cell for a cache array using half-VDD sensing is shown in Fig. 2. For a read operation, control RBACK stays low. The backup cells are not connected to the bitlines and have no impact to the read access path. Therefore, the read access time is not affected.

For the write operation, the timings of control signals MISSW, EQB, wordline (WL), RBACK, BSWITCH and SETBACK for STORE with MRUMISS is shown in Fig. 3. At the beginning of the store cycle, the interna...