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High Performance Word Decoder for Hpnp Cells

IP.com Disclosure Number: IPCOM000035395D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Canada, M: AUTHOR [+2]

Abstract

The Word Decoder (Fig. 1) provides excellent AC drive during both selection and deselection of wordlines and at the same time provides a wordline swing which is independent of power supplies and tracks with needed write margins.

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High Performance Word Decoder for Hpnp Cells

The Word Decoder (Fig. 1) provides excellent AC drive during both selection and deselection of wordlines and at the same time provides a wordline swing which is independent of power supplies and tracks with needed write margins.

The key feature of the word decoder in Fig. 1 is the clamping network and overdrive control (transistors 7-11, resistor 4). The clamping network (transistors 7,8,9,11) provides a deselect level which

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tracks very well with the select level (wordlines high) and the margin needed during write operation. The calculation of wordline swing and write margin are shown for the word decoder in Fig. 2.

The control on wordline swing reduces the tolerance on performance since the time to move the wordlines is a significant portion of delay in a memory chip. Also, the control on write margin, allows for a larger environmental operating window. For a given process and temperature range, this means the design will work under greater variations of power supply and power supply noise.

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Fig. 3 shows how the AC drive of this word decoder can be calculated. The overdrive control provides a path for this AC overdrive current during DC conditions. The power consumed in providing this AC overdrive is inversely proportional to the deselect performance of the word decoder. The power consumed due to providing the clamping network is proportional to the AC overdrive current times the mirror...