Browse Prior Art Database

Technique for Preventing Accidental Writes to EEPROM Memory During Power Sequencing

IP.com Disclosure Number: IPCOM000035396D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Chang, SC: AUTHOR [+3]

Abstract

This article describes a circuit arrangement which utilizes a complementary metal-oxide semiconductor (CMOS) latch and gate to prevent accidental writes to an electronically erasable programmable ROM (EEPROM) during power sequencing periods.

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Technique for Preventing Accidental Writes to EEPROM Memory During Power Sequencing

This article describes a circuit arrangement which utilizes a complementary metal-oxide semiconductor (CMOS) latch and gate to prevent accidental writes to an electronically erasable programmable ROM (EEPROM) during power sequencing periods.

Power sequencing may result in accidental writes because the controlling logic is placed into unknown states when the power voltage is not within the operating tolerance level. Such accidental writes have been observed to corrupt EEPROM memory locations. The CMOS logic, described herein, operates to a much lower power voltage level (as low as 2 V) than the EEPROM or other control circuits (other circuits need more than 4.5 V). Since the CMOS logic operates with such a low power voltage, the contents of the EEPROM is protected regardless of power level.

The CMOS circuit for accidental write protection is shown in the drawing as used in a typical application. This application is generating the controlling EEPROM write enable signal (-EEPWRTC) with a logic module built with bipolar logic 1. Such logic is not guaranteed for function below 4.5 V.

The -EEPWRTC signal is fed into one input of the CMOS "OR" gate 2 and the second input of the gate is connected to the CMOS latch 3 output signal (- WRTGAT). This signal is used to gate off any potential accidental assertions of the -EEPWRTC signal. Since both the -EEPWRTC and the -WRTGAT signals are negative active, the "OR" gate acts to logically "AND" them together and produces an active low output signal (-EEPWR...