Browse Prior Art Database

NEW CMOS STATIC RAM CELLS

IP.com Disclosure Number: IPCOM000035398D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR [+2]

Abstract

This article concerns a reduction in CMOS static RAM cell size and complexity by the combining of select and power supply functions to reduce the number of cell wires by one.

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NEW CMOS STATIC RAM CELLS

This article concerns a reduction in CMOS static RAM cell size and complexity by the combining of select and power supply functions to reduce the number of cell wires by one.

Conventional 6-device CMOS (complementary metallic oxide semiconductor) memory cells, such as that shown in Fig. 1, do not meet chip density requirements for new generation high-end system arrays due to cell wiring complexity. A total of five wiring lines (VH, VL, WL, BL and BR) are needed, for example, to connect this cell, leading to the need for a simpler cell topology, one offering better array density and yield.

Fig. 2 illustrates two new CMOS static cells (Figs. 2A and 2B) designed to this end. Fig. 2A shows a 6-device cell using PMOS (P type MOS) as bit rail pass transistors. Fig. 2B illustrates a complement design of Fig. 2A in which the PMOS pass transistors are replaced by NMOS (N-type MOS) devices. Since the operation of the Fig. 2A and 2B cells are basically the same in principle, only the Fig. 2A cell operation will be described in detail here.

(Image Omitted)

The Fig. 2A cell combines the power supply line VH and the word line WL (Fig. 1) into one common line WL. Only four wirings (WL, BL, BR and VL) are then needed per cell, as shown. When the cell is either metal or wiring limited, as is the case under most advanced transistor technology ground rules, a significant reduction in cell size is achieved through elimination of one wiring, resulting in hig...